Thursday, 2019-01-31

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mithrolitghost: https://github.com/SymbiFlow/prjxray-db/compare/master...mithro:master?expand=1 <- That is the latest database generation01:21
tpbTitle: Comparing SymbiFlow:master...mithro:master · SymbiFlow/prjxray-db · GitHub (at github.com)01:21
mithrolitghost: There is something going on with the HCLK fuzzers01:23
mithrolitghost: They don't seem to be running properly...01:24
litghostIs it just https://github.com/SymbiFlow/prjxray/issues/568 ?01:24
tpbTitle: Parallel build does not build all the targets · Issue #568 · SymbiFlow/prjxray · GitHub (at github.com)01:24
whatnickmithro: which host board are you using for Xray fuzzing ? Looking at setting up the fuzzer , since I have the headless xilinix toolchain already.01:24
litghostIf you re-run make at the fuzzer root?01:24
litghostwhatnick: Fuzzing only requires vivado01:25
mithrowhatnick: You don't really use a "board" for X-Ray01:25
litghostIt's purely software01:25
mithrowhatnick: If you want to *use* the toolchain to produce bitstreams for designs that is a totally different thing01:26
whatnickI have the headless toolchain set-up and taking space on my machine. Planning to put it to good use if possible.01:29
whatnickIf it is to bitstream only and back analysis of that I can keep running that ...01:30
whatnickIs the input vhdl manually generated ? auto-generated by the fuzzer ?01:30
mithrowhatnick: No VHDL involved here - do you mean Verilog?01:30
whatnickAgain my lack of knowledge there .... off to read fuzzer flow ...01:31
mithrowhatnick: What are you trying to do?01:31
whatnickhttps://prjxray.readthedocs.io/en/latest/db_dev_process/overview.html is right location01:31
tpbTitle: Overview Project X-Ray documentation (at prjxray.readthedocs.io)01:31
whatnickHelp out with mapping the xilinix board and get off the proprietary toolchain I have the Mimas board. From your talk it is mostly usable ?01:32
mithrowhatnick: Most of the Mimas boards are Spartan 6 based. Do you have a Mimas A7 or an older Mimas / Mimas V2?01:33
whatnickI did the fupy build for it using the prop toolchain over pycon 2018, aiming to get x-ray to the point where I can do the same with OS chain. I have the V201:34
mithrowhatnick: The V2 is a Spartan 6 based board. The Spartan 6 it is not supported by Project X-Ray or SymbiFlow at all01:35
whatnickAaahh ...01:36
whatnickokay time to get a new board ..01:36
mithrowhatnick: SymbiFlow is also not ready for doing FuPy stuff on any Xilinx board yet either01:36
mithrowhatnick: Yosys+nextpnr works fine with FuPy on the iCE40 parts01:37
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whatnickI only have the flea for ecp5 and an ice40 stick ..01:39
whatnickstepping back the overall goal is to do high speed ADC + Maths on FPGA to capture instantenous AC power usage and appliance finger printing ...01:40
whatnickIt does not have to support Fupy, but will make it easier to iterate ...01:40
whatnickI have some ice40 parts + ADC as well from Olimex ..01:41
whatnickhttps://www.olimex.com/Products/FPGA/iCE40/iCE40-ADC/open-source-hardware01:42
tpbTitle: iCE40-ADC - Open Source Hardware Board (at www.olimex.com)01:42
whatnickand - https://www.olimex.com/Products/FPGA/iCE40/iCE40HX1K-EVB/open-source-hardware01:42
tpbTitle: iCE40HX1K-EVB - Open Source Hardware Board (at www.olimex.com)01:42
whatnickbut I don't think the 1K is big enough for Fupy01:42
whatnickThis may be better - https://www.olimex.com/Products/FPGA/iCE40/iCE40HX8K-EVB/open-source-hardware01:43
tpbTitle: iCE40HX8K-EVB - Open Source Hardware Board (at www.olimex.com)01:43
mithrowhatnick: I suggest we move to the #timvideos channel as this isn't really symbiflow related01:47
whatnickSure ...01:48
whatnickI was also working on getting the ECP5 I have going ... would that be relevant ?01:49
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whatnickdaveshah: I have started working on the ECP5-25F sample here https://github.com/whatnick/prjtrellis/tree/master/examples/soc_fleafpga01:56
tpbTitle: prjtrellis/examples/soc_fleafpga at master · whatnick/prjtrellis · GitHub (at github.com)01:56
whatnickPulled the lpf file from the manufacturer sample01:56
whatnickWill need to make other relevant changes to account for 25F in makefile I assume, as well as openocd01:57
whatnickThis "../../misc/basecfgs/empty_lfe5um5g-45f.config --textcfg [email protected] --um5g-45k" targets 45f01:59
mithrowhatnick: Getting ECP5 stuff into the TimVideos LiteX-BuildEnv would be super cool, but again the #timvideos IRC channel would be the best place for that03:29
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mithrolitghost: https://github.com/SymbiFlow/prjxray/issues/582 -- I'm pretty sure its an issue in the Makefile at https://github.com/SymbiFlow/prjxray/tree/master/fuzzers/100-dsp-mskpat but I don't understand the file enough to see what the problem is03:54
tpbTitle: mask_dsp_l.db file seems to be invalid · Issue #582 · SymbiFlow/prjxray · GitHub (at github.com)03:54
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OmniMancerIs there a particular reason for the version of Vivado that the Project X-Ray readme.md says to install?08:39
mithroOmniMancer: Other versions don't wokr09:06
mithrolitghost: Latest db build - https://github.com/SymbiFlow/prjxray-db/compare/master...mithro:master09:08
tpbTitle: Comparing SymbiFlow:master...mithro:master · SymbiFlow/prjxray-db · GitHub (at github.com)09:08
mithrolitghost: Any idea what is going on with the artix7/tile_type_BRAM_L.json file?09:12
mithrokgugala: Do you have any idea about the parallel make issue?09:18
OmniMancerWhat is the most reasonable way to install that version of Vivado?09:18
mithroOmniMancer: Download it from the Xilinx website and install it?09:22
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kgugalamithro: TBH I'm starting to suspect a make bug - there seems to be some kind a race condition between the targets generated with fuzzer macro10:13
kgugala*some kind of a race condition10:13
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kgugalaI have random results in each run10:16
mithroI think we should make the output of the fuzzers more readable / less verbose so you can better understand what is actually going on10:38
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kgugalait is visible what is going on - some fuzzers were newer run10:52
kgugalano matter the fact that they are in the makefile10:52
kgugalafor some reason make decided that those should not be run10:53
kgugalathe missing part of the DB is because some fuzzer didn't have a chance to produce it10:53
kgugalathis is why I suspect make itself10:54
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sxpertwhat would be the proper command lines to generate a basic design from a simple .v file11:04
mithrokgugala: Do you know how to run make in debug mode?11:12
mithrosxpert: Hrm? If your asking how to create a bitstream from a simple verilog file for an ice40 I recommend asking in the #yosys or ##openfpga channels11:13
sxpertok11:14
* sxpert heads there11:14
kgugalamithro: yes, I know11:38
kgugalaI'll check what is happening there11:39
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litghostmithro: > Any idea what is going on with the artix7/tile_type_BRAM_L.json file? => This is a symptom of https://github.com/SymbiFlow/prjxray/issues/13418:11
tpbTitle: The way sites are named in Tile.get_instance_sites is broken · Issue #134 · SymbiFlow/prjxray · GitHub (at github.com)18:11
litghostBasically the way we are extracting BRAM and DSP names from the specific to generic and generic to specific is broken18:11
litghostIt's critical to fix, but it would be nice to do at some point18:12
litghostSorry, it's not critical to fix18:47
litghostOpps18:47
mithrokgugala: Sounds like you deserve cake?23:10
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