Friday, 2019-01-18

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nats`plop08:57
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nats`hey cool litghost thanks for the merge :)15:23
nats`\o/15:23
nats`my 7th commit15:23
digshadowfyi back from travels if anyone is waiting on me for something16:02
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nats`litghost, any thing I should do quickly ?19:10
nats`I can't remember what was the "road map"19:10
litghostRefactor 072 and 074 to share what is common19:10
litghoststart with the flags we added to 07419:10
litghostI refactored the post-processing, it's much faster now and uses less memory19:10
litghostso mostly just finish cleaning up 072/07419:11
nats`oky I can move the pool in the utils.py ?19:13
nats`I need to add argument to 072 too19:13
nats`nothing else more important in short term ?19:13
litghostNo, after that I'd say pick up something that interests you19:14
litghostWe have plenty of the parts that are uninvestigate, XADC, MCMM, PCIE, IOB19:14
litghostBRAM too19:15
litghosthttps://github.com/SymbiFlow/prjxray/issues/47719:15
tpbTitle: BRAM interconnect muxes are missing · Issue #477 · SymbiFlow/prjxray · GitHub (at github.com)19:15
nats`litghost, where should I start when i'll do that ? because I don't even know how you "invetigated"19:22
nats`but I'm interested in MMCM because I tinkered a lot with it on artix19:22
litghostdigshadow is a better person to talk with.  However they already started the MMCM, so maybe that will provide enough of a hint.19:23
litghosthttps://github.com/SymbiFlow/prjxray/tree/master/fuzzers/031-cmt-mmcm19:24
tpbTitle: prjxray/fuzzers/031-cmt-mmcm at master · SymbiFlow/prjxray · GitHub (at github.com)19:24
litghostI haven't taken a look at the state of the MMCM, but we are looking for two things19:24
litghost1) Can all of the MMCM parameters be expressed by the segbits output from the fuzzers?19:24
litghost2) Is there an MMCM specific routing that needs a fuzzer?19:24
digshadow2  yes I think19:25
litghost1) is an exercise in comparing https://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/7series_hdl.pdf for the MMCM against the output from the fuzzer19:25
digshadowBut 50 is pretty generic. We might be able to cover using it19:25
litghostIt's also worth noting that the MMCM fuzzer is not part of the root make, so at a minimum adding it to the root Makefile and check the fuzzer for stability issues is useful work19:27
litghostOnce 1) and 2) is done, then it needs to be added to symbiflow-arch-defs19:27
litghostBRAM example of doing this is here: https://github.com/SymbiFlow/symbiflow-arch-defs/pull/32119:27
tpbTitle: WIP: Initial XC7-BRAM support in VPR. by litghost · Pull Request #321 · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com)19:27
nats`oky :)19:35
nats`I'll annoy digshadow after fixing 072/074 :)19:35
digshadownats`: ping me once you are ready. In the meantime I'll check in with the mmcm guy19:37
mithroMorning everyone20:23
mithrolitghost: Do you need me to look at anything?20:23
litghostmithro: Not at this time20:27
litghostFYI, pushing a database update for artix7/kintex7 is a good plan20:27
litghostzync7 is close, but I heard from kgugala that fuzzer 058 failed20:28
litghosthowever that might be the last zync7 failure before an initial zync DB can be published20:28
nats`https://github.com/SymbiFlow/prjxray/commits/master <= litghost I was syncing my repo and I saw something weird in commit my 074 commit seems to have been applied two time oO20:36
tpbTitle: Commits · SymbiFlow/prjxray · GitHub (at github.com)20:36
nats`uhhmm is it me or when i source the env now I don't have (env) prefix int he terminal anymore20:42
nats`that was pretty usefull20:43
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nats`litghost, I'm updating the 072 to be like 074 PR that and only after i'll split the pool function I would like to have functionnal block in case we need to rollback20:48
litghostsounds good20:49
litghostI only see the 074 once?20:49
nats`you have my commit20:50
nats`and then upper there is your commit saying merging PR20:50
litghostare you referencing to the merge commit (https://github.com/SymbiFlow/prjxray/commit/4efea261ddb6d279847a7299da7c8876d79b8271)20:50
tpbTitle: Merge pull request #526 from natsfr/master · SymbiFlow/[email protected] · GitHub (at github.com)20:50
nats`maybe i don't understand what that means20:50
nats`yes20:50
litghostgithub creates a merge commit when pulling PR's20:50
litghostthat's all20:50
nats`ah oky20:51
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mario_Hello lads, at 35c3 I've seen your talk and waving for help and just listened to the interview on the hackaday podcast. And (i think tim was it) said it on 35c3 and the interview said that people with an spartan-6 would be cool to help documenting the bitstream. I do have a cheap chinese fpga board from ebay with a spartan-6 xc6slx9 on it. Is it possible for me to help porting that or is it even worth it?20:57
mario_I only got into fpgas last semester, but it really got me and I think i want to learn more about them20:57
sorearthere are I think 3 semi-active projects to study s6.  hardware doesn't really help here, most of the process is feeding thousands upon thousands of verilog designs into ISE and correlating the input with the resulting bitstreams21:04
mario_Is there any point where i can read up more on this or is this https://github.com/SymbiFlow/prjxray the best place?21:13
tpbTitle: GitHub - SymbiFlow/prjxray: Documenting the Xilinx 7-series bit-stream format. (at github.com)21:13
soreari'd say your best bet is to ask random people on here21:14
mario_Okay thank you. My head can't handle that right now, but i hope in a few days/weeks. Just gotta get my head straight again21:17
nats`maybe we should add (env target) in the terminal prompt when sourced it could help I always wonder which terminal is sourced21:17
sorearmaybe mwk21:18
nats`mwk ?21:19
sorearIRC user, posted a s6 thing recently21:20
nats`ah sorry didn't see you were discussing with mario_21:21
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mithrosorear: I actually think the s6 stuff is mostly blocked behind someone doing -> https://github.com/YosysHQ/yosys/issues/44822:23
tpbTitle: Spartan 3/6 support with ISE backend? · Issue #448 · YosysHQ/yosys · GitHub (at github.com)22:23
nats`mithro, I saw a new project poped recently in my github feed22:26
nats`can't find it... I should have followed it22:32
nats`I have a weird fail in "make format"22:38
nats`if [ -e env/bin/activate ]; then . env/bin/activate; fi; find . -name \*.py -and -not -path './third_party/*' -and -not -path './.git/*' -and -not -path './env/*' -and -not -path './build/*' -print0 | xargs -0 -P $(nproc) yapf -p -i22:38
nats`xargs: yapf: No such file or directory22:38
nats`Makefile:52: recipe for target 'format-py' failed22:38
nats`make: *** [format-py] Error 12722:38
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mithronats`: make env ?22:40
mithronats`: What was the project about?22:41
nats`about an open source toolchain for xilinx serie 6 and 322:41
nats`the author has an eastern europe name if I remember correctly22:41
nats`I never run make env22:42
nats`ahhh you're right22:42
nats`I erased my repo to clean it that's why :)22:43
nats`thanks22:43
mithroThere are a bunch of bitstream stuff for Xilinx s622:44
mithrobut the missing part is the synthesis + place and route22:45
nats`mithro, https://github.com/koriakin/prjleuctra22:45
tpbTitle: GitHub - koriakin/prjleuctra: Reverse engineering tools and chip database for ISE-era Xilinx FPGAs. (at github.com)22:45
mithronats`: Oh, interesting - they seem to have an approach for generating the tiles which is somewhere I think SymbiFlow might be heading....22:51
nats`apparently the guy is inspired by prjxray22:52
nats`it quote it in readme22:52
nats`litghost, https://github.com/SymbiFlow/prjxray/pull/555 <= I made the same change to add argument to the 072 fuzzer, if you could do a run to compare output that would be cool :)22:53
tpbTitle: Adding modular arguments for parallel Fuzzer 072 by natsfr · Pull Request #555 · SymbiFlow/prjxray · GitHub (at github.com)22:53
nats`he sha1 smart I forgot that -_-22:53
nats`let me few minutes to regenerate it and compare22:54
mithronats`: Yeah22:54
mithronats`: Still the big part that is missing is the Yosys side...22:55
nats`to be honnest I still don't know the general architecture of this project :)22:55
mithronats`: https://usercontent.irccloud-cdn.com/file/zziYOZqG/image.png22:58
nats`sure I saw that but I don't understand why S6 couldn't be supported by Yosys after reverse22:59
litghostIt can, but someone has to do that work23:00
daveshahSupport in Yosys is orthogonal to bitstream stuff23:01
daveshahI'm pretty sure s6 did work to some extent in Yosys once, although maybe there has been bitrot23:01
nats`uhhmm the PNR needs to be tuned to target ?23:01
litghostYosys doesn't do PNR, it does synthesis23:02
nats`uhh sure it's logic in fact23:02
nats`synthesis and PnR needs that23:02
nats`oky I think I get the idea23:02
nats`if we start a work on Serie 6 and 3 I would certainly help but I don't like those serie they have so many flaws23:03
daveshahSynthesis just needs to know about the primitives23:03
nats`the serie 7 seems perfect in comparison :)23:03
daveshahAnd in general the vendors document them reasonably well23:03
nats`ok :)23:03
nats`so basically you're saying a lot of work need to be done on a part with no reverse and "only" writing the good interface in Yosys23:04
nats`?23:04
litghostYes and no.  Implementing the techlibs are the first step.  Lowering the synthesized output then may require further mapping for the PnR tooling.  For example DRAM primatives can be considered multiple placable units23:06
nats`oky I get the idea23:07
mithronats`: bitstream documentation for the s6 is not currently the long pole for s6 support. Someone needs to do the work in Yosys first and then PnR....23:09
nats`I would like to help but I'm really too ignorant for that :)23:09
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nats`litghost, I apparently have a problem sha1 is not the same !23:59
nats`I'm surprised i'll check why23:59

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