Thursday, 2019-01-03

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BryceSchroeder_Wow, what a pain in the butt it is to try to get the free lattice diamond license that was supposed to come with the eval board I bought01:12
BryceSchroeder_it's a complete nightmare, it wouldn't recognize my company email, and when I tried to contact their support with gmail I got an automatic message saying it was being ignored because it was from gmail01:13
BryceSchroeder_FOSS tools can't happen fast enough :/01:13
hedgebergyeah, tbh.02:29
hedgeberglike, foss fpga tools lack a lot of features and I'm still happy to use them over the pro tools02:29
hedgebergits just completely unreasonable how bad the pro tool licensing and usability are.02:30
zkmsthe open source tools are pretty much the reason i actually was able to learn fpga things ;-;02:30
BryceSchroeder_I think these companies are doing themselves a disservice since their tools only work with the ICs they sell02:33
BryceSchroeder_really the tools should be free and they should just sell chips and IP cores, imho.02:34
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digshadowhey hedgeberg06:48
digshadowLet me know if you need anything to get started with prjxray06:48
digshadownoopwafel: were you able to make progress?06:52
hedgebergoh hey you already spoke to john about the fact im planning to contrib on xray?06:52
hedgebergand, yeah, will let you know, just atm im task juggling06:52
hedgebergim in the rare "remove things from the todo list" mood, instead of the opposite06:53
hedgebergso im checking things off06:53
digshadow(this is john)06:53
digshadowGotcha, so for now you are mostly lurkijng?06:53
hedgebergoooooh that makes sense07:14
hedgebergI figured your username would be like, jdm or something? or for some reason I figured you weren't on irc? no idea why I made that assumption07:15
hedgebergand, yeah, rn just lurking while I try to get as much checked off of my todolist before I go back to work next monday.07:16
hedgebergfeel like I have more free time while working than less >.<07:16
hedgebergthat being said, if I work on this anywhere, it will quite possibly be while I'm at work, since my place of work (or at least my group there) encourages using free time for self research projects07:17
hedgebergits infosec, so like, any breadth-learning is appreciated if you can just insinuate that it may come in useful down the road07:19
hedgebergand if theres one thing ive learned over the last few years its that freaking everything is a vulnerability surface07:20
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noopwafeldigshadow: productive for my understanding, not so much for prjxray so far :)07:59
digshadowhedgeberg: cool let me know then08:01
digshadownoopwafel: gotcha08:01
noopwafeldigshadow: is the way you hooked xadc into tilegrid a good example for how to hack something in?08:08
noopwafelI realize I could just ask you to do it.. :-) but trying to piece together how this works is good for me08:08
digshadownoopwafel: its not a bad place to start, but I don't think it LOCs because there is only one in the ROI08:11
noopwafelinspecting bitread output is already helpful to work out baseaddr and confirm things are kinda as expected for the GTP08:11
digshadowmaybe a good project to start with would be to convert BRAM to the new style08:11
digshadowwe know that its going to break outside of the ROI (there is a ticket)08:11
digshadowI also know that is pretty straightforward, like XADC08:12
digshadow(new tilegrid style)08:12
digshadowthis would also provide you with a known good tilegrid.json that you could check before / after08:12
tpbTitle: tilegrid: BRAM breaks on full part · Issue #342 · SymbiFlow/prjxray · GitHub (at
noopwafelstupid question time, 'full part'?08:16
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tpbTitle: Rename Artix 7 directory to something "Xilinx Series 7" · Issue #310 · SymbiFlow/symbiflow-arch-defs · GitHub (at
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noopwafel(I mean I saw the comment about the PCIE block cutting out some BRAM, just want to make sure that this is not meant to target 200T or something)08:21
mithrodigshadow: I gave you edit access to
tpbTitle: Project X-Ray - File Diagram - Google Drawings (at
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mithrodigshadow: Would be good to check the diagram on the left side08:43
mithromgielda[m]: Take a look at too08:43
tpbTitle: Project X-Ray - File Diagram - Google Drawings (at
digshadownoopwafel: we run in a "region of interest" currently, a subset of a full FPGA08:48
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digshadowif you are able to run a fuzzer, open up a .dcp in vivado. You'll see a purple box upper left08:49
digshadow(assuming you are doing artix7)08:49
digshadowmithro: I think ffconfig is part of the CLB08:50
digshadowwe should rename all clb fuzzers to have clb in the name08:50
digshadowoh nvm I misread your diagram08:50
noopwafelyeah, I saw the env variables for ROI :)08:51
digshadowI'm still a little confused about your left/right column though. should bram-data and bram-config be together there?08:52
digshadownoopwafel: if those were expanded for the full chip, bram tilegrid breaks08:52
noopwafel(btw what do the numbers in the fuzzer directory names mean? they're just categorization and otherwise arbitrary other than the run order?)08:52
digshadownoopwafel: they are for orgnization only. They are meaningless, other than generally fuzzers that must be run first have lower numbers08:53
noopwafelthanks :)08:56
mithrodigshadow: I think the we should do a bit of fuzzer renaming....09:16
mithrodigshadow: Maybe XXX-tiletype-XXXX ?09:23
mithrodigshadow: The right column is "pips" the left column is "config"09:24
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mithroacomodi: ->  alias cdb='cd $(pwd | sed -e"s,$(git rev-parse --show-toplevel),$(git rev-parse --show-toplevel)/build," -e"s,build/build,,")'10:13
digshadowmithro: sure, that naming scheme works for me11:08
digshadowdo you have any idea the pricing they are targeting on that ("maker friendly pricing")11:12
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digshadowmithro: filed
tpbTitle: Clean up fuzzer names · Issue #438 · SymbiFlow/prjxray · GitHub (at
mithrokgugala: The rebuild of Yosys will be here ->
tpbTitle: Travis CI - Test and Deploy with Confidence (at
mithrodigshadow: No idea on pricing12:07
digshadowmithro: there was also at least one jab there asking for FOSS tools12:08
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torgaxHow do I get started devving for FPGA's with OSS software? Want to write a CPU.18:31
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bitmorse_if you're a beginner, you could start by looking at the concepts (e.g. here if you're more advanced, check out and the environment - i use tinyfpga bx board and a radiona ULX3S ECP5 fpga, as they are supported at the moment.20:29
tpbTitle: Nandland: FPGA, VHDL, Verilog Examples & Tutorials (at
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