Wednesday, 2019-01-02

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hedgeberghello! JDM told me this would be a good place to connect with the dev team about contributing07:37
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hedgebergyeah this is a much lower-density channel than #yosys07:54
mithrohedgeberg: Yes!08:06
mithrohedgeberg: About to head into a meeting but will be around a bit later if you have questions08:08
hedgebergi mean im not working on this rn, but ill let you know when im starting my first to-do task mithro08:12
hedgebergand, thanks!08:12
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mithroThe DRAM tests can be found at -- as far as I know they all work. litghost was going to move onto the BRAM tests which would be in -- would be good to verify that someone else can get the DRAM tests running too11:55
tpbTitle: symbiflow-arch-defs/artix7/tests/dram at master · SymbiFlow/symbiflow-arch-defs · GitHub (at
sorearI'm annoyed that we're using "DRAM" for two unrelated things in FPGA documentation11:57
mithrotmichalak: ^11:57
mithrosorear: Distributed RAM verse external DDR RAM?11:58
sorearwish we could reserve DRAM for efforts to document the ecp5 DQSDLL blocks and whatever Xilinx has, and come up with a different term like Async RAM or LUT RAM for that thing11:58
sorearprobably too late11:58
sorearmaybe DisRAM11:59
sorearyes, distributed RAM versus external DDRx RAM11:59
mithrotmichalak: To generate images -> do cd ~/github/SymbiFlow/symbiflow-arch-defs/build/artix7/primitives/slicel then type "make <tab>"11:59
daveshahI don't think anyone ever uses DRAM for DQS primitives etc?11:59
mithrotmichalak: You'll get something like "make"12:00
daveshahIf nothing else that SDRAM doesn't need them12:00
mithrosorear: I almost always say DDR RAM12:00
daveshahWhat would be confusing is an FPGA with built in DRAM12:00
mithrodaveshah: inbuilt DDR RAM? :-P12:00
daveshahie the Anlogic parts with die stack SDRAM12:01
mithrodaveshah: The two ram types in iCE40UP5K is alway confusing :-P12:01
daveshahPretty sure I've seen a FPGA with DDR2 in package12:02
sorearxilinx and altera have talked a lot about HBM/HMC for high end parts but idk if anything ever shipped12:03
sorearbut re. DRAM I'm thinking more litedram and the overwhelming external computer industry context12:03
daveshahEG4D20 has 128Mb DDR in package12:07
sorearnow we just need one with eDRAM12:08
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daveshahThat would be fun12:16
daveshahI wonder if we will ever see commercial FPGAs with dynamic config memory?12:16
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sorearit seems like a better fit for gain cells (2T/3T using "parasitic" gate capacitance of a dedicated read transistor) than traditional 1T1C DRAM12:24
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mithrotmichalak: You want to add this alias to your ~/.bash_aliases or ~/.bash_rc13:08
mithroalias cdb='cd $(pwd | sed -e"s,$(git rev-parse --show-toplevel),$(git rev-parse --show-toplevel)/build," -e"s,build/build,,")'13:08
mithrolets you quickly switch between the build and non-build at the same directory level13:09
mithrotmichalak: So it looks like the stuff in the dram directory just tests to check that VPR can place and route those primitives13:11
mithrotmichalak: The actual place which creates something which runs on the device is it seems13:12
tpbTitle: symbiflow-arch-defs/ram_test.v at master · SymbiFlow/symbiflow-arch-defs · GitHub (at
mithrotmichalak: See the top module here ->
tpbTitle: symbiflow-arch-defs/top.v at master · SymbiFlow/symbiflow-arch-defs · GitHub (at
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tpbTitle: SymbiFlow Architecture Definitions symbiflow-arch-defs 0.1 documentation (at
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tpbTitle: SymbiFlow Architecture Definitions symbiflow-arch-defs 0.1 documentation (at
mithromgielda / tmichalak:
tpbTitle: SymbiFlow Architecture Definitions - File Diagram - Google Drawings (at
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mithromgielda: Is that helping?15:06
mgieldayup, thx15:10
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mithroHi kgugala!15:37
mithromgielda: Take a look at and
tpbTitle: vtr-verilog-to-routing/atom_netlist.h at master+wip · SymbiFlow/vtr-verilog-to-routing · GitHub (at
mithromgielda: It has pretty nice documentation in those files which turns up *nowhere* when you search for it15:39
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mithroNow _thats_ a diagram ->
tpbTitle: SymbiFlow Architecture Definitions - File Diagram - Google Drawings (at
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