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felix_ | the line numbers in sdi are basically off by one *sigh* the line number in the end of active video packet belonging to one line has the line number corresponding to the next line. wasn't sure if the diagrams in the itu recommendation and the standard were just weird, but nope, the simulation shows that this is indeed what gets transmitted over the wire | 16:49 |
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RexOrCine | Hi felix_ - Last time you said "PhotonSDI code is currently existing and being developed in several building blocks that will be connected together and tested as a whole eventually, and interfacing between the plugin module and the camera is work in progress." | 19:55 |
RexOrCine | If you were to give an update now would it be much the same? | 19:55 |
felix_ | i made some progress on friday and today, but there's no big groundbreaking change yet that's worth announcing | 20:27 |
RexOrCine | Thanks. | 20:29 |
RexOrCine | Is it a case of your have to perform a number of tests and once those are done it'll be ready for use? | 20:30 |
RexOrCine | your having* | 20:31 |
RexOrCine | More complicated no doubt. | 20:32 |
felix_ | most parts i worked on when i was in vienna in i think november fall in that category; i'm currently working on the timing generator, but that definitely isn't in a state yet where i'm near the testing phase | 20:35 |
felix_ | hooked up part of the proprietary refernce code in a testbench to have a look if i read the itu recommendation right (that recommendation is much more useful than the smpte spec, but i think i already rated about that ;P | 20:36 |
felix_ | for the stuff i wrote in vienna i'll also write a testbench to do some a-b tests before integrating that into the test design | 20:36 |
felix_ | finding bugs in the simulation is easier than on hardware and the sort of bugs i'll probably encounter there will mostly be easy to spot in a short simulation | 20:37 |
felix_ | but yeah, not really much new stuff to report from my side, but quite a bit of work in progress stuff | 20:38 |
felix_ | but at least i get to work on this again after not really getting around to do that for too long | 20:39 |
se6astian | thats great indeed! | 20:40 |
felix_ | my guess would be that i can also spend the rest of this week on photonsdi. can't guarantee though | 20:41 |
se6astian | wonderful! | 20:46 |
RexOrCine | I'm getting a lot of approaches from hot women asking "What about SDI?! What about SDI?!" I said "Felix... He's the one with the magic touch" ... that's why I came in asking... the hot women. | 20:47 |
felix_ | if it was in the late 80s, they probably would have been foreign agents wanting to get some information about the strategic defense initiative ;P | 20:50 |
RexOrCine | XD | 20:51 |
RexOrCine | Shame eh. It could have been any one of these - https://duckduckgo.com/?q=bond+girls&t=h_&iar=images&iax=images&ia=images | 20:52 |
tpb | Title: bond girls at DuckDuckGo (at duckduckgo.com) | 20:52 |
RexOrCine | ... well, the ones in the 80's. | 20:52 |
felix_ | hmm, should i write the timing generator in a way that we could support interlaced and progressive segmented frame formats an addition to the progressive format? progressive segmented frames is what 1080p30 over 1.5g sdi uses IIRC. interlaced formats (and overscan) are also so last century though ;P | 20:59 |
felix_ | PsF is basically transferring a full picture as an interlaced picture, but both half frames are from the same original frame | 21:00 |
felix_ | i think the 1080p30 over hd sdi is important enough that the core should be able to handle that | 21:02 |
Kjetil | you can do native p30 over SDI as well without using PsF (I hate PsF) | 21:03 |
felix_ | ah, yes, that sounds like a much better idea | 21:05 |
felix_ | how is the compatibility with existing equipment though? | 21:05 |
Kjetil | I don't think that is a big problem. PsF in itself is a solution to a problem that no longer exists, but it keeps hanging around :/ | 21:06 |
felix_ | ok. so i throw the PsF in the same bin as sd sdi and interlaced formats and just pretend that it doesn't exist | 21:07 |
Kjetil | I will have a look at what the big interfacing vendors support | 21:07 |
felix_ | yeah, getting rid of hacks that were implemented to work around some stuff usually won't go away unless the system gets a fundamental redesign, but even in these cases, that stuff tends to stay around for backward compatibility | 21:08 |
felix_ | thx | 21:08 |
Kjetil | At least for BM and AJA, the recording equipment either supports both p30 and psf30 or none off them. | 21:21 |
Kjetil | (29.97 is more common than pure 30) | 21:22 |
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felix_ | ok, so i'll probably get around implementing interlaced and psf support | 21:28 |
felix_ | i mean adding that later isn't that much of a problem anyway | 21:29 |
Kjetil | Yeah. I wouldn't prioritize it | 21:29 |
felix_ | i'll support both 30 and 30/1.001 frame rates; still prefer the former though. that one is mostly a matter of flipping some configuration bits in the clock generator | 21:30 |
Kjetil | I'm just wondering if you need something similar to a interlacing timing generator to implement 6G. Not sure how the data is formated on the link | 21:30 |
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felix_ | before working on 6g i want to get 1.5g and 3g working. i don't know about the image formats in 6g, but the encoding on the wire is basically the two variants that can also be used on 3g, but double number of virtual data pipes. ok, and some bit flipping on the sync words to prevent issues with the scrambler | 21:36 |
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