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felix_ | uh, oh, azonenberg had a look at the jitter of the mems oscillator i used for the 25 mhz for the fpga on the axiom photonsdi hw: https://i.imgur.com/SSUXrlC.png | 22:33 |
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felix_ | if i'll see issues that might be related to that device, i'll swap that with a better one for the next revision; that's easy to change | 22:37 |
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Bertl | do you expect problems with the 25MHz clock? | 22:39 |
felix_ | i don't expect problems, but if there will be problems that might be related to that, that would be the forst thing to try; can probably swap the oscillator | 22:41 |
felix_ | did you try if the fpga pll can lock to the 25mhz? if not, that would be something i'll try early in the bringup | 22:42 |
felix_ | if it locks, it'll likely be good, if not, i'll bodge another oscillator into the design | 22:43 |
RexOrCine | Do you ecpect HW to change too much? | 22:44 |
RexOrCine | ... in the foreseeable future. | 22:44 |
RexOrCine | Or is it pretty solid now? | 22:44 |
Bertl | first and foremost it is untested :) | 22:45 |
felix_ | there will be some incremental changes, but (hopefully) no bigger redesign | 22:45 |
felix_ | yep | 22:45 |
felix_ | most of the already well known bugs are fixed in git master, but for the next revision i'll need to do more of the bringup and testing of this prototype | 22:46 |
felix_ | haven't used the dsc6001 in any other design yet, but people were experiencing problems with it, so i'm at least aware of possible problems there | 22:51 |
Kjetil | The 25Mhz is only a reference for the FPGA logic? | 23:00 |
felix_ | yep | 23:02 |
felix_ | for the sdi part i'd be pretty sure that that oscillator won't work at all, but i did use some proper clock generator there ;) | 23:05 |
Kjetil | I guess we will have to measure it | 23:05 |
Kjetil | to figure out how bad it is ;) | 23:05 |
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