Thursday, 2019-03-14

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felix_uh, oh, azonenberg had a look at the jitter of the mems oscillator i used for the 25 mhz for the fpga on the axiom photonsdi hw: https://i.imgur.com/SSUXrlC.png22:33
felix_if i'll see issues that might be related to that device, i'll swap that with a better one for the next revision; that's easy to change22:37
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Bertldo you expect problems with the 25MHz clock?22:39
felix_i don't expect problems, but if there will be problems that might be related to that, that would be the forst thing to try; can probably swap the oscillator22:41
felix_did you try if the fpga pll can lock to the 25mhz? if not, that would be something i'll try early in the bringup22:42
felix_if it locks, it'll likely be good, if not, i'll bodge another oscillator into the design22:43
RexOrCineDo you ecpect HW to change too much?22:44
RexOrCine... in the foreseeable future.22:44
RexOrCineOr is it pretty solid now?22:44
Bertlfirst and foremost it is untested :)22:45
felix_there will be some incremental changes, but (hopefully) no bigger redesign22:45
felix_yep22:45
felix_most of the already well known bugs are fixed in git master, but for the next revision i'll need to do more of the bringup and testing of this prototype22:46
felix_haven't used the dsc6001 in any other design yet, but people were experiencing problems with it, so i'm at least aware of possible problems there22:51
KjetilThe 25Mhz is only a reference for the FPGA logic?23:00
felix_yep23:02
felix_for the sdi part i'd be pretty sure that that oscillator won't work at all, but i did use some proper clock generator there ;)23:05
KjetilI guess we will have to measure it23:05
Kjetilto figure out how bad it is ;)23:05
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