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| felix_ | no, every pin outputs a characteristic pattern that can be checker with a usb-uart | 10:59 |
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| Bertl | yeah, but the question is, what happens if two pins are connected? | 11:08 |
| Bertl | will that cause a short or is the signal properly handled (e.g. by using tristate instead of pulling high or very limited current, etc) | 11:09 |
| Bertl | and is the pattern generated at the same clock cycles or is there a nice shift between outputs so that you can see the overlap | 11:10 |
| felix_ | the patterns are currently all aligned | 11:13 |
| felix_ | i wouldn't expect a short between connections | 11:14 |
| Bertl | well, I wouldn't either, but that's (among other stuff) what we are testing for, no? :) | 11:15 |
| Bertl | so please, adapt the design to offset the pattern between channels and make it use tristate instead of pulling high when not active | 11:16 |
| Bertl | use a keeper to avoid unexpected edges | 11:16 |
| Bertl | also, do we get pattern on the MGTs as well? | 11:17 |
| felix_ | uh oh, i wasn't planning to have to go back to this today; have to get some other things ready before i leave for vienna :/ | 11:18 |
| felix_ | there are no mgt-related test for the board yet | 11:18 |
| Bertl | okay, so what are your plans regarding testing once you arrive? | 11:19 |
| felix_ | i'd test the interface between the module and the camera, then get the clock chip working, then get the control interface of the sdi chips working, then the gigabit transceiver stuff fo the sdi in/out | 11:23 |
| Bertl | okay, you are aware that we don't have the SDI chips on yet? | 11:24 |
| Bertl | and that it would be a good idea to test basic functionality before we add them? | 11:24 |
| felix_ | apart from that i'll work on photonsdi again; probably on the old board though. and then port it to the new board | 11:25 |
| felix_ | yes, i'm aware that the sdi chips aren't populated yet | 11:25 |
| felix_ | yeah, that's why i wrote the test | 11:25 |
| Bertl | not sure how you'll test the MGTs with that though | 11:26 |
| Bertl | anyway, is the source for your test suite available somewhere? | 11:26 |
| felix_ | https://gist.github.com/felixheld/5966c2032ae85d352b129fe574f37010 with the io standard of the differential lanes changed to IOStandard("LVCMOS25"), in axiom_photonsdi_hw.py | 11:27 |
| tpb | Title: axiom_photonsdi_hw_test.py ยท GitHub (at gist.github.com) | 11:27 |
| Bertl | how do you build it? | 11:28 |
| felix_ | sending the bytes on the different pins non-overlapping shouldn't be too hard to implement; i can try to da that later today | 11:30 |
| felix_ | when you have installed migen, litex and photonsdi (photonsdi with the io standard changed and no termination selected) in in virtualenv and have sourced the vivado config, you can just run axiom_photonsdi_hw_test and it'll generate you the bitstream | 11:31 |
| felix_ | should work with a recent python3 | 11:35 |
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| felix_ | hm, the gtp bringup sort-of depends on the bringup of the si* chip | 13:34 |
| Bertl | the si chip is there, no worries :) | 13:35 |
| Bertl | but if you mean for test purposes, you can drive the GTP PLLs from the fabric as well | 13:36 |
| Bertl | so no need for the special GTP clock input | 13:36 |
| felix_ | i'd say though that if the fpga bringup was successful (fpga power rails work, fpga is configurable and the flash can be used), and all power rails work, my biggest concerns regarding the hardware would be eliminated and i'd say that the risk of putting the sdi chips on there shouldn't be too high | 13:36 |
| felix_ | true that | 13:36 |
| Bertl | how long are you going to stay? | 13:37 |
| felix_ | hmm, might it be an option to put one sdi transmitter on the board if the fpga bringup was successful? | 13:37 |
| felix_ | i'll arrive on thursday and leave on monday | 13:37 |
| Bertl | okay, so if initial testing on thursday is just fine, then we can add the missing parts on friday or saturday | 13:38 |
| felix_ | my main reason not to put the sdi chips on the board at first was that i wasn't 100% sure if the power rails and the fpga works | 13:38 |
| felix_ | sounds like a plan | 13:38 |
| felix_ | but yeah, since i'll probably do most of the photonsdi development on one of the old modules, this shouldn't be a blocker anyway | 13:39 |
| Bertl | one SDI chip and later the rest is probably too tricky | 13:40 |
| felix_ | ok | 13:40 |
| Bertl | but we'll see and decide | 13:40 |
| felix_ | yep | 13:40 |
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