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| *** se6astian|away is now known as se6astian | 08:10 | |
| *** Bertl_zZ is now known as Bertl | 09:58 | |
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| *** se6astian|away is now known as se6astian | 18:39 | |
| se6astian | felix_: when should we start with a first prototype production run of the hardware? | 18:50 |
|---|---|---|
| se6astian | or are there any more reviews/changes pending? | 18:51 |
| felix_ | i planned to go through https://github.com/azonenberg/pcb-checklist/ but realistically won't get around to do that before the 20th september. i already went through part of the list, but not everything | 19:27 |
| tpb | Title: GitHub - azonenberg/pcb-checklist: Sign-off review checklist for PCB designs (at github.com) | 19:27 |
| felix_ | i also didn't check the pinouts again; double-checked them when i made the symbols though | 19:28 |
| felix_ | Bertl: would it cause you much pain and work to first only populate part of the boards and if that works populate the rest | 19:29 |
| Bertl | depends on the parts :) | 19:31 |
| felix_ | i'd suggest to only populate the power supply, the fpga and its flash and test if that works and populate the sdi chips and the clock generator later | 19:33 |
| Bertl | got an url with a recent design screenshot for? | 19:34 |
| Bertl | *for me | 19:34 |
| felix_ | let me search in the backlog | 19:36 |
| felix_ | https://i.imgur.com/Ufjuoeb.jpg is the latest version i found | 19:37 |
| felix_ | after that there were only slight changes near the hdbnc connectors | 19:37 |
| felix_ | the chips and their position didn't change that much after that | 19:38 |
| Bertl | so what are chips you want to populate later? U201, U301, U901, U1101 and? | 19:39 |
| felix_ | and u402 | 19:40 |
| felix_ | or maybe populate u402 with the fpga; it's not a that expensive chip | 19:41 |
| Bertl | that should be doable | 19:42 |
| felix_ | but the sdi chips are around 32 euros per chip; so i wouldn't populate them before we know that the rest of the board works | 19:42 |
| felix_ | (that's the motivation behing my question) | 19:42 |
| felix_ | i had a brief look at the pcb again and i have already fixed everything that i wanted to fix | 19:49 |
| felix_ | i'm not aware of other things that need to be changed | 19:50 |
| Bertl | what are the PCB requirements? | 19:50 |
| felix_ | i used the design rules for the 4 layer oshpark process | 19:50 |
| Bertl | excellent | 19:51 |
| felix_ | might be good if you could check if the goemetry for the 100 ohm differential lines and the 75 ohm sdi lines are correct | 19:51 |
| Bertl | how did you calculate them? | 19:51 |
| felix_ | i used the saturn pcb toolkit | 19:51 |
| Bertl | should be good enough for a first test | 19:52 |
| felix_ | i'll generate a fresh set of gerber files, since i'm not sure if the gerber files i have here are for the current pcb version | 19:53 |
| Bertl | OSHpark can process KiCad directly | 19:53 |
| Bertl | so maybe just try there if the upload works | 19:53 |
| felix_ | ah, didn't know that | 19:53 |
| Bertl | it's also a good check to go through the renderings there | 19:54 |
| felix_ | haven't used anything but gerber files ini the last 6 years for ordering pcbs | 19:54 |
| Bertl | yeah, if it doesn't work with the KiCad files, you have to generate Gerbers anyway :) | 19:55 |
| felix_ | http://sigsegv.notmysegfault.de/intern/AXIOM-photonSDI-hw.zip are the gerbers for the current design version that is on github | 19:56 |
| felix_ | and the current schematics http://sigsegv.notmysegfault.de/intern/AXIOM-photonSDI-hw.pdf | 19:57 |
| felix_ | when you've ordered the board, i'll push the files to the git repo and add a v1.0 tag | 19:58 |
| felix_ | with files i meant the pdf export of the schematics and an archive with the gerber files | 19:59 |
| felix_ | well, the gerber files if you want me to do that; the schematics are probably useful for more people than the gerbers | 20:00 |
| felix_ | oh, i forgot to post the link to the archive with the gerber files. here it is: http://sigsegv.notmysegfault.de/intern/AXIOM-photonSDI-hw.zip | 20:02 |
| felix_ | oh, already linked those. i'm not that much awake any more at the moment... | 20:03 |
| felix_ | but yeah, it would be good if you could have a quick look with a gerber viewer and if it loooks good to you, go ahead and order one set of 3 boards | 20:05 |
| felix_ | the drc of the pcb design completes witout errors or warnings | 20:05 |
| felix_ | oh, wait, found a problem | 20:08 |
| felix_ | N_LVDS_4 near the board ege connector | 20:09 |
| felix_ | i uploaded new gerber files under the same url | 20:20 |
| Bertl | make sure the kicad files are up-to-date as well | 20:20 |
| felix_ | i pushed the change to https://github.com/felixheld/AXIOM-photonSDI-hw | 20:21 |
| tpb | Title: GitHub - felixheld/AXIOM-photonSDI-hw: SDI interface board for the apertus° AXIOM beta camera (at github.com) | 20:21 |
| felix_ | hmm, let me add a version number to the zip file | 20:21 |
| felix_ | just to prevent sending the wrong file to oshpark | 20:22 |
| felix_ | http://sigsegv.notmysegfault.de/intern/AXIOM-photonSDI-hw-v1.0.0.zip | 20:23 |
| felix_ | i'll go home now; will look in the irc channel in maybe 30 minutes again. have to get up early tomorrow though... | 20:26 |
| *** se6astian is now known as se6astian|away | 21:04 | |
| felix_ | i read through the design checklist again | 21:17 |
| felix_ | i only double-checked the footprints myself when i designed them (most aren't board proven!) | 21:17 |
| felix_ | another thing that might be worth a look is the solder paste aperture reduction for the voltage regulator pads; mostly those of the two ldos. beware that those are soldermask defined though | 21:20 |
| felix_ | doesn't look too wrong to me, but might be good, if you could have a look at that | 21:21 |
| felix_ | good night | 21:21 |
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