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| se6astian | Good morning felix_, how is the routing going? | 08:29 |
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| felix_ | i have more or less routed everything that can be routed before the placing is finalized. still working on the global placement, to get the board smaller. the routing is the easy part; the placing the tricky one ;) | 14:31 |
| felix_ | can the eeprom also store the plugin module hardware revision and feature set populated or should i rather add some locations for pull-up/down resistors on some spare fpga pins? | 14:37 |
| felix_ | or is the plan only to produce fully populated boards and no partially populated boards that e.g. only have one sdi output and no sdi input or legacy synchronization input? | 14:42 |
| felix_ | ah, i need to improve the axiom connector; that's currently the default pcie x1 edge connector from the kicad library, which isn't nice | 14:58 |
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| se6astian | the eeprom is envisioned to store a lot of information about the plugin moldule not just name and version/revision | 19:25 |
| se6astian | the actual structure is not defined yet | 19:25 |
| se6astian | but the eeprom has plenty of space | 19:26 |
| felix_ | ok | 19:26 |
| se6astian | partial population does make sense I guess | 19:26 |
| felix_ | the module will be about 7cm long (including the pcie-style connector) | 19:29 |
| felix_ | won't get much smaller that this | 19:29 |
| se6astian | can you share a preliminary layout of the whol module ? | 19:30 |
| se6astian | screenshots | 19:30 |
| felix_ | i ripped apart some parts yesterday to optimize some stuff, but sure i can share a screenshot later | 19:32 |
| se6astian | great | 21:10 |
| felix_ | http://i.imgur.com/RCjbOGw.png | 21:14 |
| felix_ | connectors are from to sdi in, 2x sdi out, legacy sync in | 21:14 |
| felix_ | the footprints of the crystal and crystal oscillator are still missing and the footprints of the voltage regulators and the pcie-style connector still need some work | 21:16 |
| felix_ | the line at the top is 7cm long | 21:17 |
| felix_ | but yeah, the pcb will not get much smaller and the general position of things won't drastically change any more | 21:21 |
| felix_ | well, some millimeters at the top and botten still can be shoved off, so that it will fit the form factor | 21:22 |
| Kjetil | Is there any actual benifit to placing the DC-blocking caps that close to the connector? | 21:32 |
| Kjetil | I guess U1101 is the sync separator. Could probably save a bit by using a cheaper connector for it? | 21:34 |
| felix_ | yeah, the sync seperator doesn't need some super high end connector | 21:41 |
| Kjetil | I'm guessing a lot more thermal vias are recommended on the EGP on the jitter cleaner | 21:42 |
| Kjetil | "Use no fewer than 25 vias from the center pad to a ground plane under the device" | 21:43 |
| Kjetil | (Details at this stage) | 21:43 |
| Kjetil | Remember that you don't really need to care about polarity on SDI so you can swap around the high speed serial lines to ease routing | 21:49 |
| felix_ | yep | 21:54 |
| Kjetil | Are there missing some rubber bands between the sync sep. and the FPGA? | 21:56 |
| felix_ | i ripped apart a lot of the fpga connections yesterday and haven't fully reconnected them, so yes, a lot of the fpga connections are missing at the moment | 21:58 |
| Kjetil | have you connected hsout to both the jitter cleaner and the fpga? | 21:59 |
| felix_ | hsync from the sync seperator? | 22:00 |
| felix_ | there should also be a connection to the fpga | 22:00 |
| Kjetil | yes | 22:00 |
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