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felix_ | are there any special requirements for the fiducials on the boards? just 3 per board side or also local fiducials near the qfn parts with 0.4mm and 0.5mm pitch? | 15:44 |
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felix_ | oh and did i get it right that the placement of the high speed axiom connectors is on a non-metric grid? | 15:45 |
Bertl_oO | they really can't be on any reasonable grid | 15:47 |
Bertl_oO | the fingers for the plugins are placed in such way that two single slot modules have a small gap between them and that they can be palced in any slot | 15:48 |
Bertl_oO | the total height is the same as the microzed (so imperial) | 15:48 |
Bertl_oO | the dual slot modules are basically two single slot modules 'combined' into one board | 15:49 |
felix_ | ah. yep, now that makes much more sense to me | 15:49 |
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se6astian | fiducials in the general area of the corners would be great | 17:06 |
se6astian | 0.5mm circles work best | 17:07 |
se6astian | no special fiducials near the qfn parts required | 17:08 |
felix_ | ok | 17:13 |
felix_ | hmm, i might fir a sync seperator chip on the board to be able to synchronize to a non-sdi timing reference. should i look into that? | 18:46 |
felix_ | *fit | 18:46 |
Kjetil | support for analog sync would probably not be a bad thing if used for live tv production | 19:33 |
se6astian | could the alternative timing sync also come from a signal connected to/from the microzed? | 19:41 |
felix_ | should be no problem. when using the sdi input as reference clock, the clock gets recovered in the gtp rx cdr and passed to the si5342 via a differential output from the fpga. not sure if i should also add a differential lane from the optional clock output of the sdi equalizer chip; might be a routing congestion problem though | 20:14 |
felix_ | since i'm not entirely sure how the gtp pll behaves when the input frequency shifts a bit, i added a fixed frequency crystal oscillator that could optionally be populated and used as reference clock for the rx cdr | 20:15 |
felix_ | and when in free-running mode the si5442 output can be set to the needed frequency. in the mode where it tracks a reference clock input, it keeps also outputting the same frequency even when the reference clock stops | 20:33 |
Kjetil | Do you have a way of providing sync back to the beta mainboard? | 20:35 |
felix_ | there are 12 lvds lanes and 2 currently unused single ended signals between the module and the camera | 20:37 |
felix_ | from the 8 io pins on the south axiom connector 4 are used for jtag, 2 for uart between the module and the camera and so two remain | 20:38 |
felix_ | the uart pins are normal fpga pins, but are planned to be always used as slow-ish sideband interface | 20:39 |
Kjetil | since you don't have a framestore in the FPGA on SDI module you would need to make sure the video output from the mainboard is timing aligned | 20:40 |
felix_ | yep. just route the clock from the output module via one of the lvds pairs to the camera | 20:41 |
felix_ | adding some ddr3 chip as framebuffer wouldn't be routeable on the 4 layer board | 20:41 |
Kjetil | that would just give you frequency lock, you need phase lock. So you need to send frame start as well | 20:42 |
felix_ | i'd just use one of the two remaining single ended signals to signal a frame start and some short fifo to compensate for possible jitter | 20:43 |
felix_ | the other option would be to have the camera generate the right timing and only do the encapsulation on the sdi module and when synchronizing to an external clock reference use a frame begin (or frame end) strobe | 20:48 |
Kjetil | should work | 20:50 |
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