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| felix_ | after digging through a whole lot of datasheets, i'd say that the SI5342B is our clocking chip. the SI5344B is footprint-compatible for our application, so if one is out of stock, we could use the other one; i hope though that this won't be necessary... | 13:09 |
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| se6astian | https://octopart.com/search?q=SI5342B&start=0 | 13:09 |
| se6astian | 12-15€ per pc | 13:09 |
| se6astian | but SDI is the expensive stuff :D | 13:10 |
| felix_ | i am still unsure if it's a problem to lock to an sdi input without some other clock source for the rx part of the gtp though; if the pll in the gtp quad stays locked, it should work, if it doesn't we're in trouble ;) workaround would be to add a crystal oscillator on the second gtp clock input and use that for sdi rx | 13:10 |
| felix_ | yeah, around 13 euros per cjip in single quantities. some of the chips i looked at were much more expensive | 13:11 |
| felix_ | what i like about this chip can lock to an external signal (the recovered clock from the gtp rx part), continues to output a nice signal when the external signal stops, is really low jitter and that it's only one chip | 13:13 |
| felix_ | without a sdi input signal, it can be configured to either output the 148.5 mhz or the 148.5/1.001 mhz and with an sdi inout signal it can synchronize to that, so only one chip with one output for all frequencies | 13:17 |
| se6astian | sounds good | 13:19 |
| felix_ | the module can't output signals with normal and franctional line rate at the same time on its two connectors, but i don't think that this would be a real limitation | 13:23 |
| se6astian | agreed | 13:30 |
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| felix_ | hmm, i wonder if it's a good idea to power the the 3.3v rails of the clock chip and the sdi output chips from the 3.3v rail from the axiom connector. for the two vcco rails of the fpga it should just work, but i'm unsure about the clock/sdi stuff | 18:39 |
| Kjetil | It should be silent | 18:50 |
| Kjetil | you might be able to get away with a PI-filter on the rail. But a having a separate LDO might be preferable | 18:55 |
| felix_ | yeah, that would be the better solution. i'm not entirely sure how to do the trade-off between cost, area, complexity and numbers of revisions before the board works reliably ;) i hope to have the board working right in the first revision. i might be a bit too careful, but both bugs in the power supplies and some signal integrity issues have already bitten me in previous projects | 19:02 |
| Kjetil | If you have room for it.. layout both and use whatever works | 19:06 |
| Kjetil | you probably need the pi filters between the SDI output drivers and the clock chip regardless if they share a 3.3v rail | 19:16 |
| *** se6astian|away is now known as se6astian | 19:28 | |
| felix_ | yep, i have/will put lc filters in all analog rails | 19:34 |
| *** se6astian is now known as se6astian|away | 21:44 | |
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