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| se6astian | hi felix_, any news from the last week? | 10:03 |
|---|---|---|
| felix_ | not much; had to take care of some other things and caught a cold; planned to work the weekend on it, but felt too sick :/ | 10:53 |
| se6astian | :( | 10:59 |
| se6astian | I was hoping we would have pcbs sent off for production some time ago already.... | 10:59 |
| se6astian | how is the plan for this week then? | 11:00 |
| felix_ | yeah, i also wanted to have the pcb done :/ i'm in the office again on friday | 11:02 |
| se6astian | what are the remaining steps? | 11:07 |
| felix_ | i need to figure out what to use for clocking the transceivers, create some missing footprints and do most of the routing | 11:16 |
| se6astian | right, fingers crossed for friday! | 11:19 |
| felix_ | maybe i'll have some time to do some reseach regarding the clocking before that; except the exact mapping of the fpga pins that's the only thing that's not done in the schematic yet | 11:21 |
| felix_ | routing the 3,3v gpios of one axiom connector and the high speed lanes of both connectors to a seperate fpga io bank each seems to work btw | 11:31 |
| felix_ | the bga escape routing of one bank will be a bit tricky, but so far i'd say that it's possible without having to make too big compromises on the signal integrity | 11:33 |
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