| *** tpb has joined #photonsdi | 00:00 | |
| *** futarisIRCcloud has quit IRC | 03:00 | |
| *** Bertl_zZ is now known as Bertl | 04:58 | |
| *** se6astian|away is now known as se6astian | 07:44 | |
| *** Bertl is now known as Bertl_oO | 09:31 | |
| *** se6astian is now known as se6astian|away | 09:48 | |
| *** se6astian|away is now known as se6astian | 11:02 | |
| se6astian | hi felix_: how are things going? | 11:33 |
|---|---|---|
| *** RexOrCine|away is now known as RexOrCine | 14:24 | |
| felix_ | i'm currenty working on the footprints, but that involves more yak shaving than i hoped :/ | 14:34 |
| se6astian | so do you think a version to order before you leave in two days is realistic? | 14:40 |
| *** se6astian is now known as se6astian|away | 14:40 | |
| felix_ | it's gonna be tough; i could also work on that when i'm in india, but i'd try to get as much ready before that, since i don't have my workstation in india and layouting pcbs on a laptop is rather meh | 14:45 |
| *** RexOrCine is now known as RexOrCine|away | 14:49 | |
| felix_ | oh and i have most of today and tomorrow to push the project forward | 14:49 |
| *** se6astian|away is now known as se6astian | 17:22 | |
| se6astian | felix_: fingers crossed then -> gogogo :D | 17:23 |
| Bertl_oO | push it! | 17:24 |
| felix_ | the eeprom on the north connector isn't populated on the existing boards, but should still be included in the design, right? | 19:24 |
| felix_ | oh and which voltages are vcc and vccio on the high speed connector? | 19:26 |
| felix_ | is vccio the 1.8v the io bank connected to the lvds pairs should be connected to? | 19:27 |
| felix_ | ah, seems so. still the question what vcc (pin B13) is | 19:29 |
| felix_ | oh and what the pwrgd pin does on the axiom connector | 19:30 |
| felix_ | Bertl_oO: ^ | 19:30 |
| Bertl_oO | eeprom only one on a dual slot plugin | 19:37 |
| Bertl_oO | vccio is 2.5V by default but can be anything between 1.8 and 3.3 in theory | 19:38 |
| Bertl_oO | VCC is typically 3.3V but could go down to 2.5V | 19:38 |
| felix_ | so vccio is for the lvds pairs and vcc is for the single ended ios that are connected to the machxo2? | 19:39 |
| Bertl_oO | yep, precisely | 19:40 |
| Bertl_oO | realistically the MachXO GPIOs will always be 3.3V and also can be configured in the new power board | 19:40 |
| Bertl_oO | so the plugin can provide information about the requirements and the camera can adjust | 19:41 |
| felix_ | ok | 19:41 |
| Bertl_oO | for the pwrgd pin we haven't decided yet | 19:42 |
| Bertl_oO | i.e. it was suggested to provide some kind of 'reset' and/or power good feedback from the plugin | 19:42 |
| Bertl_oO | till now the pin is basically unused (and unconnected) | 19:43 |
| felix_ | ok | 19:44 |
| felix_ | is it guaranteed that the 5v pin is always powered when vcc/vccio is powered? | 19:45 |
| Bertl_oO | no, they are basically independent | 19:45 |
| Bertl_oO | i.e. 5V can be powered down (on recent betas) with VCCIO/VCC up | 19:45 |
| Bertl_oO | (and vice versa) | 19:45 |
| felix_ | uh oh | 19:46 |
| felix_ | so i should rather generate all voltages from the 5v rail? | 19:46 |
| felix_ | hm, i don't have a 2.5v rail on my board yet though | 19:47 |
| Bertl_oO | depends on what you plan to do with the voltages | 19:53 |
| Bertl_oO | they (VCCIO/VCC) are designed to power IO banks and level converter | 19:53 |
| Bertl_oO | so if you have a dedicated bank for interfacing, you can simply hook up the VCC/VCCIO rail to your plugin and that's it | 19:54 |
| Bertl_oO | the 5V rail is basically if you need anything else/independent from the I/O rails | 19:55 |
| Kjetil | I guess it might more be a question of current per rail? | 20:08 |
| Bertl_oO | VCCIO should work up to 3A | 20:09 |
| Bertl_oO | VCC at least 2A | 20:09 |
| Bertl_oO | but the limit for 5V is 3A as well (actually less) | 20:10 |
| Bertl_oO | note that you won't fit 3/2/3A in the total power budget though | 20:10 |
| felix_ | hm, i'd have to have a look if it's ok for the fpga to have some io rails powerde while the core isn't powered; only had the case that some io isn't always powered while the core is always powered | 20:14 |
| Kjetil | You will also have coolingissues with 20W+ going into the module | 20:14 |
| Bertl_oO | felix_: any sequencing could be controlled by the camera | 20:16 |
| Bertl_oO | (at least on modern power boards that is) | 20:16 |
| Bertl_oO | on the older ones, the 5V rail is 'always' on while the VCC/VCCIO can be controlled | 20:16 |
| felix_ | ah, ok, so just use vcc/vccio for the two io banks facing the camera and the 5v rail for everything else | 20:17 |
| Bertl_oO | should work that way | 20:18 |
| Bertl_oO | if you have 'other' 3V3 banks to power, you could 'require' VCC to be 3V3 and use that too (for example) | 20:18 |
| felix_ | the configuration io bank and the flash are also 3.3v | 20:20 |
| felix_ | so i can use vcc instead of the regulator on the sdi board, right? | 20:20 |
| felix_ | most power will be drawn from the 1.0 and 1.8v rails anyway that are powered by those little tps modules from the 5v rail | 20:21 |
| Bertl_oO | yeah, low speed I/O banks do not draw much power | 20:22 |
| Bertl_oO | LVDS channels on the other hand ... | 20:22 |
| Bertl_oO | but powering the core and MGTs from 5V is probably a good idea | 20:23 |
| felix_ | on the mgts: i'm still not sure if i could use the fpga 1v rail and some filtering or use a dedicated stepdown or use an ldo from the 1.8v fpga aux rail | 20:24 |
| Bertl_oO | 1.8V to 1V is not that much, so an LDO would be an option | 20:25 |
| felix_ | in the designs i did, i always used a dedicated stepdown, but on a 400 euro fpga the few euros for the stepdown modules just didin't matter and i had plenty of board space | 20:25 |
| felix_ | and 1.8v to 1.2v for the second gtp rail | 20:25 |
| Bertl_oO | what's the 1.2V used for? | 20:26 |
| felix_ | uh, the gtp need 1.0 and 1.2v | 20:26 |
| felix_ | mgtavcc and mgtavtt | 20:26 |
| Bertl_oO | yeah, but what's the power there? | 20:27 |
| Bertl_oO | is it termination (high power) or reference (low power)? | 20:27 |
| felix_ | mgtref is another pin | 20:29 |
| Kjetil | LDOs will probably give you good analog performance. But as Bertl_oO says it depends on the current requirements | 20:35 |
| felix_ | meh, to get some values for the current on the lines, i'd need to use the power estimator spreadsheet that only works in microsoft excel. iirc it was like 300mA per gtp per rail | 20:36 |
| felix_ | ah, mgtavtt is for the termination and mgtavcc is for the rest of the gtp | 20:40 |
| felix_ | the vcc/vccio of both slots is connected together on the axiom or are that different rails? | 20:44 |
| Bertl_oO | they are independent rails but with some constraints | 20:46 |
| Bertl_oO | VCC is basically a separate rail for each plugin | 20:48 |
| Bertl_oO | VCCIO is the same rail as used for the ZYNQ banks 13/34/35 | 20:49 |
| Bertl_oO | note that each bank has a separate regulator on the power board | 20:49 |
| felix_ | ok, so i only use power from one of the connectors | 20:51 |
| Bertl_oO | I presume you connect all LVDS channels from the plugin interfaces? | 20:51 |
| Bertl_oO | so you need to basically 'specify' a common voltage requirement for both banks (for the module) | 20:52 |
| Bertl_oO | unless you are connecting them to two different banks, in which case you could simply split the bank voltage | 20:52 |
| Bertl_oO | but in any case, if you are using LVDS, the bank voltage does not matter much | 20:53 |
| felix_ | hmm, i have to see if i can put them on different rails | 20:53 |
| Bertl_oO | (besides that it has to be enough for LVDS :) | 20:53 |
| felix_ | hehe, true that | 20:53 |
| felix_ | on the i2c eeprom: why is there both a resistor to vcc and gnd? or is the one to vcc not populated? | 21:08 |
| Bertl_oO | the idea here is to populate both (which disabled the write protection) and once the EEPROM is properly programmed, simply remove the one to GND | 21:10 |
| Bertl_oO | *disables | 21:10 |
| Bertl_oO | of course, if you want the EEPROM to stay configurable, you can just leave it on or not populate the one to VCC | 21:11 |
| felix_ | ah, ok. so i leave both in the design | 21:11 |
| felix_ | hmm, i'll probably connect the xadc supply to the fpga rails, since i have quite a bit of routing congestion in that area. sure, the values from the xadc will probably have a lot of noise, but its only application might be getting a rough device temperature, so i'd say that this shouldn't be a big problem | 21:34 |
| felix_ | so basically dropping the suggested filter for the supply and connecting it directly to the digital supply | 21:36 |
| *** se6astian is now known as se6astian|away | 21:37 | |
| *** futarisIRCcloud has joined #photonsdi | 23:54 | |
Generated by irclog2html.py 2.13.1 by Marius Gedminas - find it at mg.pov.lt!