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| *** se6astian|away is now known as se6astian | 09:07 | |
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| felix_ | hmm, it would be good to have the pinout/documentation (including voltage levels) of the plugin module slots on the website as image or pdf (at elast i didn't find it) | 17:13 |
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| felix_ | the levds lanes were 1,8v and the io lines 3,3v, right? | 17:13 |
| felix_ | *lvds | 17:13 |
| Kjetil | lvds is lvds :) | 17:25 |
| Kjetil | but i guess they can be used single ended as well | 17:26 |
| felix_ | yep. but if someone uses a bitstream that hat those pins in a wrong mode, the fpga shouldn't get damaged due to too high voltage | 17:27 |
| felix_ | i've already (partially) fried enough fpgas with too high voltage on the inputs... but that was only one fpga when i was i think 13. didn't take into account that a multimeter only shows an average voltage and 50% duty cycle of 5v are 2,5v which was the voltage of the io bank the clock was connected to. but yeah, mistakes you only make once ;P | 17:30 |
| Kjetil | hehe | 17:31 |
| Kjetil | I don't think the FPGA will get damaged by setting the wrong voltage mode in the bitstream. It is more dependent on the voltage supplied to the bank | 17:32 |
| felix_ | it depends. setting a much lower voltage in the bitstream than supplied might also cause damage in the io blocks | 17:33 |
| felix_ | the other way around the slew rate will just be much lower | 17:33 |
| felix_ | but the problem i meant was if some output is configured as not-lvds and drives the output hight with a higher voltage than the io bank voltage of the other fpga | 17:35 |
| Kjetil | sure | 17:47 |
| Kjetil | but the protection diode on the other fpga will likely save it | 17:48 |
| Kjetil | If there is a current limiter on the output of the transmitting part | 17:49 |
| Kjetil | But having the documentation readily available is good | 17:50 |
| Kjetil | I prefer a format easily parsable by a machine if one wishes to do any kind of automatic verification | 17:51 |
| *** Bertl_oO is now known as Bertl_zZ | 19:42 | |
| *** se6astian|away is now known as se6astian | 19:59 | |
| felix_ | uh oh, the clock of the config flash is in about the worst place in the bga for routing on a 4 layer board :/ but i think worst case is that i have to limit the programming clock to 33mhz; which is still ok when using a quad io flash | 21:08 |
| *** RexOrCine|away is now known as RexOrCine | 21:38 | |
| *** se6astian is now known as se6astian|away | 22:30 | |
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