Monday, 2022-10-03

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animatrixhello05:28
animatrixi'm trying to build verilog rtl of litedram for arty05:28
animatrixi'm not sure what to do though, can anyone help me out ?05:29
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animatrixplease help me out06:35
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_florent_animatrix: you can use this: https://github.com/enjoy-digital/litedram/blob/master/examples/arty.yml10:29
_florent_and do litedram_gen arty.yml10:29
_florent_then customize the user ports to your need: https://github.com/enjoy-digital/litedram/blob/master/examples/arty.yml#L35-L5210:30
_florent_and re-run10:30
animatrixyeah i found an issue with some data of how to use10:51
animatrixbtw10:51
animatrixwhy does litedram use ISERDES in networking mode and not memory mode10:52
animatrixi see people reading the input dqs strobe and using that as a clock to the DQ iserdes but that doesn't seem to be what's going on here10:52
animatrixalso memory mode is only capable of 1:4 and not 1:8 like networking, i'm not sure what the compromises are of using either in this situation10:52
animatrix2. I tried simulating litedram for 100us with a ddr3 model, i see a lot of 'X' on the address lines. The controller keeps repeating a precharge all and doesn't do the init sequence and init_done never becomes true.10:54
animatrixhttps://ibb.co/VjNfw9q10:55
tpbTitle: image — ImgBB (at ibb.co)10:55

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