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| animatrix | hello | 05:28 |
|---|---|---|
| animatrix | i'm trying to build verilog rtl of litedram for arty | 05:28 |
| animatrix | i'm not sure what to do though, can anyone help me out ? | 05:29 |
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| animatrix | please help me out | 06:35 |
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| _florent_ | animatrix: you can use this: https://github.com/enjoy-digital/litedram/blob/master/examples/arty.yml | 10:29 |
| _florent_ | and do litedram_gen arty.yml | 10:29 |
| _florent_ | then customize the user ports to your need: https://github.com/enjoy-digital/litedram/blob/master/examples/arty.yml#L35-L52 | 10:30 |
| _florent_ | and re-run | 10:30 |
| animatrix | yeah i found an issue with some data of how to use | 10:51 |
| animatrix | btw | 10:51 |
| animatrix | why does litedram use ISERDES in networking mode and not memory mode | 10:52 |
| animatrix | i see people reading the input dqs strobe and using that as a clock to the DQ iserdes but that doesn't seem to be what's going on here | 10:52 |
| animatrix | also memory mode is only capable of 1:4 and not 1:8 like networking, i'm not sure what the compromises are of using either in this situation | 10:52 |
| animatrix | 2. I tried simulating litedram for 100us with a ddr3 model, i see a lot of 'X' on the address lines. The controller keeps repeating a precharge all and doesn't do the init sequence and init_done never becomes true. | 10:54 |
| animatrix | https://ibb.co/VjNfw9q | 10:55 |
| tpb | Title: image — ImgBB (at ibb.co) | 10:55 |
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