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| pepijn_web | I'm trying to build linux on vexrisc but somehow my toolchain setting isn't making it through | 10:31 |
|---|---|---|
| pepijn_web | ah found the problem | 10:35 |
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| pepijn_web | hmmm can I poke litex_term at a soc without writing any extra code? | 13:46 |
| pepijn_web | oh wait I don't think this SoC has serial and everything set up so what am I even doing | 13:52 |
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| lge07 | hello! i'm doing some benchmarking of an soc design with the sim mode, and i was wondering --- is there a way of building the simulation model and supporting software once, and then being able to use the output to test different programs? | 23:37 |
| lge07 | right now, i'm re-invoking the build / run process to run each test in the benchmark suite, but as a result newlib gets re-compiled every time, as does everything in the software folder and the Verilator model, even though the SoC options do not change, only the test program. | 23:37 |
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