| *** tpb <[email protected]> has joined #litex | 00:00 | |
| *** Flea86 <Flea86!~maomao@user/Flea86> has joined #litex | 00:40 | |
| *** lexano <[email protected]> has quit IRC (Ping timeout: 276 seconds) | 01:18 | |
| *** pbsds3 <[email protected]> has quit IRC (Ping timeout: 244 seconds) | 01:19 | |
| *** CarlFK <[email protected]> has joined #litex | 01:35 | |
| *** CarlFK1 <[email protected]> has joined #litex | 01:59 | |
| *** CarlFK <[email protected]> has quit IRC (Ping timeout: 260 seconds) | 01:59 | |
| *** CarlFK1 <[email protected]> has quit IRC (Ping timeout: 260 seconds) | 02:48 | |
| joshua_ | cc discord; is there a more idiomatic way to spell this in Migen / LiteX? https://gist.github.com/jwise/115d2ba1b4d3e8cb3529ab1764d24461 | 02:53 |
|---|---|---|
| joshua_ | (I wish to hand-instantiate a DFF with very careful control over what the RTL looks like so that I know that I get exactly one DFF and that the synthesis tool gives me one DFF with the reset pins hooked up the way I want) | 02:54 |
| *** CarlFK <[email protected]> has joined #litex | 03:21 | |
| *** whitequark[cis] <whitequark[cis]!whitequark@2a01:4f8:c012:5b7:0:1:0:4> has joined #litex | 03:24 | |
| whitequark[cis] | with my Amaranth hat on: write the entire thing in Verilog and instantiate it | 03:24 |
| *** Degi_ <[email protected]> has joined #litex | 03:25 | |
| whitequark[cis] | I don't think this is even sound, as you make no effort to reserve {nam}_q in ns | 03:25 |
| whitequark[cis] | (or, the way I could actually write it, though it's very different from your approach, is to branch on the platform you're synthesizing for, and emit a platform primitive for Xilinx, Lattice, etc, whatever you care about) | 03:26 |
| *** Degi <[email protected]> has quit IRC (Ping timeout: 260 seconds) | 03:26 | |
| *** Degi_ is now known as Degi | 03:26 | |
| joshua_ | I was kind of thinking of doing that as an Instance, yes. my hope was I guess that the idiomatic thing I was truly looking for was that someone had already written a DFF special that I just hadn't seen | 03:26 |
| whitequark[cis] | since by the time you need that precise of a control you typically tie yourself to a specific platform or few platforms | 03:26 |
| joshua_ | (the specific thing I am trying to achieve here is having a register in my design that is combinationally reset as a S/R latch when the PLL loses its mind, so that the system can assert some safe GPIO state even if the clock never ticks again) | 03:27 |
| joshua_ | I am not super worried about soundness since I am doing this thing exactly once | 03:28 |
| whitequark[cis] | I mean Migen emits everything into one global namespace | 03:28 |
| whitequark[cis] | so anything else in your design can conflict with it potentially | 03:28 |
| whitequark[cis] | re: S/R latch, do you basically want a clock domain with async reset (which Migen notoriously doesn't support)? | 03:29 |
| joshua_ | in theory, yes, in practice, 'pll_unlock_dff_q' is an unusual sounding name for anything other than what I am trying to do | 03:29 |
| whitequark[cis] | because I don't think many FPGAs support S/R latches, and even fewer FPGA toolchains bother exposing them | 03:30 |
| joshua_ | yes, clock domain with async reset seems fine. I did not like it because this is not "really" a clock domain or a global set/reset that makes sense for anything else | 03:31 |
| whitequark[cis] | any distinct async control set of a DFF is a clock domain | 03:31 |
| whitequark[cis] | (even if you just change the async reset pin) | 03:32 |
| whitequark[cis] | (async reset is just one time use clock) | 03:32 |
| joshua_ | I know that Xilinx will infer latches from incomplete `always @(*)` (and scream the entire time). I have no idea if Efinix's tools will or what happens if you try it. you can implement it by hand with a LUT if you are brave, I suppose | 03:33 |
| whitequark[cis] | Xilinx will infer D-latches | 03:33 |
| whitequark[cis] | but you are mentioning an S/R latch, which is fairly different | 03:33 |
| whitequark[cis] | that being said, your actual code shows a DFF with async reset, which is completely fine | 03:36 |
| joshua_ | I guess I would implement a S/R latch in RTL as a D latch. and indeed, this is a DFF with async reset because I did not want to play games with incomplete `always @(*)` and I could express it this wa ytoo :) | 03:37 |
| whitequark[cis] | there is just that annoying terminological ambiguity over whether a DFF is a "latch" | 03:37 |
| joshua_ | (in this case, making the S synchronous and the R async) | 03:37 |
| whitequark[cis] | I think that's not really an S/R latch even? | 03:37 |
| whitequark[cis] | I think to make a DFF into an SR latch you'd fix D at 1, set ARST_VALUE to 0, use posedge clk and posedge rst, and now your CLK input is S and RST input is R | 03:38 |
| whitequark[cis] | (we could also take the discussion of what is a man^W latch elsewhere since we're clearly on the same page) | 03:39 |
| joshua_ | in this case if I were implmenting it as a S/R latch, I would say that S = ~pll_locked, R = self.pll_unlock_lockout_reset.re, and in this case, R is made synchronous so it's sort of a latch and sor tof a flop, but yes, indeed, we are broadly on the same page | 03:39 |
| joshua_ | (I am aware that self.pll_unlock_lockout_reset.re would be quite bad as an async reset if it were not constrained to exactly be the Q pin of a flop, though!) | 03:40 |
| joshua_ | Diogenes: behold, a latch! | 03:41 |
| *** pbsds3 <[email protected]> has joined #litex | 04:00 | |
| *** CarlFK <[email protected]> has quit IRC (Ping timeout: 252 seconds) | 04:04 | |
| *** TMM <[email protected]> has quit IRC (Quit: https://quassel-irc.org - Chat comfortably. Anywhere.) | 04:37 | |
| *** TMM <[email protected]> has joined #litex | 04:38 | |
| *** CarlFK <[email protected]> has joined #litex | 04:44 | |
| *** CarlFK <[email protected]> has quit IRC (Ping timeout: 245 seconds) | 04:49 | |
| *** CarlFK1 <[email protected]> has joined #litex | 05:05 | |
| *** FabM <FabM!~FabM@2a03:d604:10a:9a00:f4be:37d9:b762:70ba> has joined #litex | 05:30 | |
| *** CarlFK1 <[email protected]> has quit IRC (Ping timeout: 248 seconds) | 06:09 | |
| *** SpaceCoaster <SpaceCoaster!~derek@user/spacecoaster> has quit IRC (Ping timeout: 245 seconds) | 07:41 | |
| *** SpaceCoaster <SpaceCoaster!~derek@user/spacecoaster> has joined #litex | 07:46 | |
| *** feldim2425_ <[email protected]> has joined #litex | 08:41 | |
| *** feldim2425 <feldim2425!~feldim242@user/meow/feldim2425> has quit IRC (Ping timeout: 255 seconds) | 08:41 | |
| *** d_olex <d_olex!~d_olex@user/d-olex:35658> has quit IRC (Ping timeout: 260 seconds) | 09:40 | |
| *** CarlFK1 <[email protected]> has joined #litex | 10:52 | |
| *** CarlFK3 <[email protected]> has joined #litex | 10:53 | |
| *** CarlFK1 <[email protected]> has quit IRC (Ping timeout: 252 seconds) | 10:57 | |
| *** CarlFK3 <[email protected]> has quit IRC (Quit: Leaving.) | 11:43 | |
| *** CarlFK1 <[email protected]> has joined #litex | 11:43 | |
| *** CarlFK1 <[email protected]> has quit IRC (Quit: Leaving.) | 12:08 | |
| *** 047AAAZ08 <[email protected]> has joined #litex | 12:08 | |
| *** lexano <[email protected]> has joined #litex | 12:08 | |
| *** 047AAAZ08 <[email protected]> has quit IRC (Ping timeout: 260 seconds) | 12:55 | |
| *** oter <oter!5e7a0135f3@2a03:6000:1812:100::25f> has quit IRC (Remote host closed the connection) | 13:01 | |
| *** oter <oter!5e7a0135f3@2a03:6000:1812:100::25f> has joined #litex | 13:01 | |
| *** d_olex <d_olex!~d_olex@user/d-olex:35658> has joined #litex | 13:26 | |
| *** SpaceCoaster <SpaceCoaster!~derek@user/spacecoaster> has quit IRC (Quit: Bye) | 14:06 | |
| *** SpaceCoaster <SpaceCoaster!~derek@user/spacecoaster> has joined #litex | 14:06 | |
| *** shorne_ <[email protected]> has joined #litex | 14:09 | |
| *** shorne <[email protected]> has quit IRC (Ping timeout: 260 seconds) | 14:11 | |
| *** TMM <[email protected]> has quit IRC (Quit: https://quassel-irc.org - Chat comfortably. Anywhere.) | 17:50 | |
| *** TMM <[email protected]> has joined #litex | 17:51 | |
| *** FabM <FabM!~FabM@armadeus/team/FabM> has quit IRC (Ping timeout: 260 seconds) | 19:17 | |
| *** peeps[zen] <peeps[zen]!~peepsalot@openscad/peepsalot> has quit IRC (Remote host closed the connection) | 20:22 | |
| *** peeps[zen] <peeps[zen]!~peepsalot@openscad/peepsalot> has joined #litex | 20:22 | |
| *** peeps[zen] <peeps[zen]!~peepsalot@openscad/peepsalot> has quit IRC (Quit: Connection reset by peep) | 20:44 | |
| *** peepsalot <peepsalot!~peepsalot@openscad/peepsalot> has joined #litex | 20:46 | |
| *** shorne_ <[email protected]> has quit IRC (Read error: Connection reset by peer) | 22:44 | |
| *** shorne <[email protected]> has joined #litex | 22:49 | |
| *** pbsds3 <[email protected]> has quit IRC (Quit: The Lounge - https://thelounge.chat) | 22:56 | |
| *** pbsds3 <[email protected]> has joined #litex | 22:57 | |
| *** pbsds3 <[email protected]> has quit IRC (Quit: The Lounge - https://thelounge.chat) | 23:31 | |
| *** pbsds3 <[email protected]> has joined #litex | 23:33 | |
Generated by irclog2html.py 2.17.2 by Marius Gedminas - find it at https://mg.pov.lt/irclog2html/!