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| whitequark[cis] | joseng: okay, so i see two kinds of violated paths in that report | 18:25 |
|---|---|---|
| whitequark[cis] | the first one is in sys_clk<>hdmi_clk. those clocks aren't intended to be related, are they? | 18:26 |
| whitequark[cis] | you need to add a set_clock_groups constraint for those domains | 18:27 |
| whitequark[cis] | the second kind is reset deassertion violation. you might want to put a BUFG on that net with a fanout of 1600 | 18:27 |
| whitequark[cis] | * on that reset net with | 18:27 |
| whitequark[cis] | sys_rt | 18:27 |
| whitequark[cis] | * sys_rst | 18:27 |
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| kw00 | hi | 20:22 |
| kw00 | I started using litex and it is great. I managed to apply some fpga configuration to colorlight board with vexriscv and run application in rust. I have colorlight hardware revision 8.2 which is not yet supported. I would like to figure out fpga pin names and pins on hub75 connectors like described here for previous revision | 20:31 |
| kw00 | https://github.com/q3k/chubby75/blob/master/5a-75e/hardware_V7.1.md and here https://github.com/litex-hub/litex-boards/blob/master/litex_boards/platforms/colorlight_5a_75e.py#L180 I found some idea to set all pins as uart tx and transmit in loop fpga pin name then read then using some logic analyzer. Does it make sense? Do you know if such project | 20:31 |
| kw00 | already exists? | 20:31 |
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