Friday, 2023-10-27

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hveclock in Litex are confusing. Anyone know how to get the current clk Signal from within a litex module?13:37
tntClockSignal()13:38
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hveIs this the same as "self.cd_sys.clk" ??13:42
tntI think so.13:42
hveI will try, tnx13:43
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hveOne more maybe: self.specials += Instance("pwm",p_WIDTH=width,... Instance("pwm", ... Is not a migen value14:27
hveI have added the verilog file using add_source with a "module pwm" 14:28
hveStupid mistake... fixed..14:56
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