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| josuah | hello joshua_ and sorry for the long wait! | 19:26 |
|---|---|---|
| josuah | > Does anyone have any suggestions for how to accomplish what I want? | 19:26 |
| josuah | yes, yes, yes! | 19:26 |
| josuah | Let me find that again... | 19:26 |
| josuah | <joshua_> Here we go! https://github.com/enjoy-digital/litex/blob/master/litex/tools/litex_soc_gen.py | 19:27 |
| josuah | this one is a command line tool | 19:27 |
| josuah | but you can also use it from a scrip with `from litex.tools import litex_soc_gen` then instantiate your own derived SoC out of it, to plug more things to it: | 19:29 |
| josuah | class YourSoC(litex_soc_gen.LiteXSoCGenerator): | 19:31 |
| josuah | then when you will build it, you will geet a Verilog file, but nothingwould be built from it. | 19:31 |
| josuah | But... you can also target a board directly, as some cores need non-portable elements to work, and even build it | 19:32 |
| josuah | and integrate the extra cores you need into LiteX instead of integrating LiteX into another project. (both are possible though) | 19:32 |
| josuah | For that, you do not need anything, use a board from https://github.com/litex-hub/litex-boards/ as a template (both the platform/ and target/ file.py) | 19:33 |
| gurki | if you already have an existing design it might be easier to integrate some small rv core by hand than to try to integrate everything into a soc generator | 19:33 |
| gurki | the latter is nice and easy until you have custom parts :3 | 19:33 |
| gurki | but this probably heavily depends on what you have in front of you :) | 19:34 |
| josuah | ^ that is a good beacon... "The little guy that did the best with what he had..." lyrics from https://www.openbsd.org/lyrics.html#41 | 19:36 |
| tpb | Title: OpenBSD: Release Songs (at www.openbsd.org) | 19:36 |
| josuah | joshua: litex_soc_gen --help | 19:37 |
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| joshua_ | josuah, ha, familiar faces from all over the internet :) I guess I coudl have asked you in the 1b2 discord then! | 21:01 |
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| joshua_ | as gurki noted I am currently going to integrate vexriscv by hand for this current design. later I think I do want to integrate things into a SoC generator that will have a bunch of top level ports for custom I/O in my design, and bind those out to register files generated by a SoC generator (it is *very* alluring to have something generate HTML documentation that I can hand to my client!). | 21:06 |
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| joshua_ | this current design I need, basically, a UART, a SPI initiator, and two registers for counters that come from logic | 21:07 |
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