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MoeIcenowy | _florent_: I cannot imagine the adjust is so simple | 00:59 |
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MoeIcenowy | My own lead to get the read latency -= 1 change (because there is RBURST (BURSTDET called by Lattice)), however for the write latency -= 1 I didn't find it (because I have no knowledge about the internal of LiteDRAM) | 01:00 |
MoeIcenowy | nickoe: not possible w/o proper primitives from Gowin | 01:03 |
MoeIcenowy | a primitive called GW_JTAG is known to exist in prim_syn.v in Gowin toolchain | 01:05 |
MoeIcenowy | but not documented at all | 01:05 |
MoeIcenowy | and GAO is surely encrypted | 01:06 |
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sensille | Hoernchen: the patch is only for the eth_clock. 30mhz is awfully low, where is the critical path? | 05:22 |
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Hoernchen | sensille, https://dpaste.org/BrVRK - apparently to a dpram? this is the unmodified "colorlite" | 07:53 |
tpb | Title: dpaste/BrVRK (Console/Bash Session) (at dpaste.org) | 07:53 |
sensille | 23ns routing, that is a long path | 07:55 |
Hoernchen | there are apparently some false paths that can be ignored - just, uh, knowing which ones are the false path is the problem | 07:56 |
sensille | do you need etherbone for your project? | 07:57 |
Hoernchen | i might, i didn't really plan to use a cpu, so it looks like the most obvious way to just have a bus | 07:57 |
Hoernchen | but i'm currently just trying to figure out what works and what doesn't work | 07:58 |
sensille | https://dpaste.org/0jxuo | 08:02 |
tpb | Title: dpaste/0jxuo (Plain Text) (at dpaste.org) | 08:02 |
sensille | colorlite.py --build | 08:02 |
sensille | (with 30mhz clock target) | 08:03 |
sensille | how do you call it? | 08:03 |
Hoernchen | literally like that | 08:04 |
sensille | with 50mhz: https://dpaste.org/q8Nq3 | 08:05 |
tpb | Title: dpaste/q8Nq3 (Plain Text) (at dpaste.org) | 08:05 |
sensille | eth clk is hit and miss | 08:05 |
Hoernchen | can you ever got to 50? | 08:06 |
Hoernchen | get | 08:06 |
sensille | diamond can get to 50, but fails in the eth path. my patch might help there | 08:15 |
sensille | but 40 should be enough? | 08:16 |
Hoernchen | i guess so | 08:16 |
Hoernchen | i'm just wondering if there ever was a way to hit those default frequencies | 08:17 |
sensille | no luck with abc9/flow3 either | 08:21 |
Hoernchen | yeah i'm currently trying some of those magic ravenslofty cookbook incantations | 08:24 |
sensille | i don't feel well running a design with failed timings either | 08:25 |
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fts-tmassey | Hello! I'm having trouble with linux-on-litex-vexriscv and a Terasic de0nano. I've downloaded to the board, I get the side-to-side LED's, but I can't communicate with it. | 14:43 |
fts-tmassey | I think it's because I need to connect to a UART via the GPIO header pins, but I don't know what pins to use! I'm happy to answer any questions I can, of course. | 14:44 |
fts-tmassey | I'm running on Debian Bookworm, with a Terasic de0-nano. Quartus 22.1free. I'm happy to provide parameters, logs, timings, etc. but you would have to help me to find these... I basically followed the bouncing ball from the readme. | 14:47 |
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jevinskie[m] | <MoeIcenowy> "and GAO is surely encrypted" <- I’d bet we can get around that little road bump if that’s what is necessary for figuring out the primitive/enabling litejtag. ;) | 14:48 |
fts-tmassey | I have also successfully used Quartus to download a quick procedure from the Terasic manual. Seeing as I see the LED's moving like I've seen in other tutorials, it seems I've successfully downloaded the FPGA code. The problem is, I can't connect to the serial interface to download the Linux kernel, etc. | 14:48 |
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fts-tmassey | Here is an issue I've created with more details: https://github.com/litex-hub/linux-on-litex-vexriscv/issues/348 | 15:52 |
fts-tmassey | Thank you for any help you might be able to provide! | 15:52 |
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josuah | hello fts-tmassey! | 16:34 |
josuah | I'm not tinkering with linux-on-litex-vexriscv but with zephyr-on-litex-vexriscv (different devboard), but close enough :) | 16:35 |
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jevinskie[m] | For de0-nano try adapting this DECA board config that uses the onboard usb blaster 2 https://github.com/litex-hub/litex-boards/blob/master/litex_boards/prog/openocd_max10_blaster2.cfg | 17:08 |
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josuah | _florent_: I will try this :) https://github.com/enjoy-digital/litex/wiki/Export-Your-Core-SoC-To-Verilog | 17:58 |
josuah | Did you have any plan for it? | 17:58 |
josuah | I thought about a board definition with a "null platform" of some kind that does not invoke any platform-specific primitive | 17:59 |
josuah | the top-level of LiteX would become a module in the user's design, with the bus exposed | 17:59 |
josuah | oh, I did not look, maybe that's already there in LiteX! | 18:01 |
josuah | _florent_: thank you for the merges by the way! | 18:16 |
josuah | We can work with a fork periodically synced with upstream for a long while, no pressure to merge anything :) | 18:17 |
whitequark[cis] | <MoeIcenowy> "and GAO is surely encrypted" <- what's GAO? | 18:44 |
whitequark[cis] | oh, Gowin Analyzer Oscilloscope IP? | 18:45 |
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whitequark[cis] | the use of GW_JTAG looks very straightforward to me, it's almost the same as the Xilinx one | 18:48 |
whitequark[cis] | btw the private keys to decrypt the Gowin IP are listed in plaintext, grep for "-----BEGIN RSA PRIVATE KEY-----" | 18:50 |
whitequark[cis] | if you wanna look at GAO IP write a few lines of openssl :p | 18:52 |
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josuah | https://panoramix-labs.fr/brilliant-labs/gowin-logic-analyzer/ | 20:13 |
josuah | whitequark[cis]: maybe they had bug when turning encryption off :D | 20:14 |
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whitequark[cis] | no it's just the implementation is like that | 20:23 |
whitequark[cis] | they're in the gwsyn.so library | 20:23 |
josuah | one would have to be in a country where reverse engineering allows as far as decrypting IPs to understand how the hardware works... | 20:36 |
josuah | even if the IP content is not included directly | 20:36 |
josuah | not sure how this all works to be honest. | 20:36 |
gurki | whitequark[cis]: thats hilarious, thanks for mentioning this :D | 20:37 |
whitequark[cis] | you just decrypt the IP and get done with it | 20:38 |
whitequark[cis] | don't tell me you've never pirated a movie either | 20:38 |
whitequark[cis] | it's no one's business what you do in the privacy of your own computer | 20:39 |
josuah | yes, but I did not write a novel out of the scenario of a pirated movie either | 20:39 |
josuah | if something needs to be integrated with open-source project for instance | 20:39 |
gurki | whitequark[cis]: im laughing about the plaintext key, not you doing whatever you do with it | 20:40 |
whitequark[cis] | yeah i was responding to josuah | 20:40 |
gurki | ah :) | 20:40 |
josuah | the question is about how to face a lawyer if that had to happen | 20:41 |
josuah | oh, nevermind | 20:41 |
josuah | if someone of the size of i.e. intel, nvidia wants me legally down, they probably do not need me to be actually stealing anything ^_^' | 20:41 |
whitequark[cis] | power does as power wants | 20:42 |
whitequark[cis] | though, i have once got a c&d from xilinx, and i'm still alive | 20:42 |
josuah | \o/ kudos on being alive, I mean it | 20:42 |
whitequark[cis] | you don't actually need to tell anyone where you know how to use GW_JTAG from | 20:44 |
Hoernchen | someone decrypts it and describes it, someone else implements it according to the docs | 20:44 |
whitequark[cis] | or you can always do a parallel construction, exactly the same thing as the state does when it doesn't want to give up sources of evidence | 20:44 |
whitequark[cis] | get it from RE, and then pretend you got it from very inspired experimentation | 20:44 |
whitequark[cis] | Hoernchen: I think this might not work in this particular case | 20:45 |
whitequark[cis] | since the person decrypting is still liable | 20:45 |
Hoernchen | in this particular case the "thing" is... not particularly unique or exciting, it should be reasonably easy | 20:45 |
whitequark[cis] | I mean | 20:45 |
josuah | I just understood all the 4chan leaks... someone needs it, someone "else" publishes it, it's out, grab it :S | 20:45 |
whitequark[cis] | I looked at GW_JTAG, I could describe it without any RE work | 20:45 |
Hoernchen | ah yes but: who is that person? imagine docs showing up somewhere... | 20:45 |
gurki | josuah: its a very, very (...) very complex topic with a lot of strong oppinions | 20:46 |
whitequark[cis] | I can trivially break Gowin encryption too but it's not enough of a challenge to bother | 20:46 |
josuah | gurki: sorry for opening the lid | 20:46 |
gurki | for me personally its a minefield im not touching with a long stick | 20:46 |
Hoernchen | the way it should not be done is the ham guys and their "reversed" ambe codec which is pretty much the dsp code decompiled and translated into c after running in the emulator.. | 20:48 |
Hoernchen | that is just tainted beyond repair | 20:48 |
whitequark[cis] | as someone who thinks almost all IP should not exist I can only admire the degree of commitment there | 20:50 |
Hoernchen | ambe is a major issue, it prevents open source DMR because you're supposed to buy a physical chip to use it | 20:52 |
whitequark[cis] | yeah, I know about ambe | 20:52 |
Hoernchen | and i'm still trying to forget all the things i never saw while not looking at the nice lattice diamond text f.. uh.. binary blobs | 20:56 |
whitequark[cis] | i thought diamond ships ip as netlists? | 21:03 |
whitequark[cis] | and whatever the hell is that cursed simulation format | 21:03 |
Hoernchen | oh not the ip | 21:05 |
Hoernchen | the part and bit descriptions | 21:05 |
Hoernchen | long, long chains of boolean equations that tell you which bit does what | 21:06 |
Hoernchen | the lattice ip that is used by sinplify was rsa bsafe protected at the time, so.. slightly more difficult than grepping for the key | 21:06 |
Hoernchen | i.e. the tri speed ethernet mac | 21:07 |
whitequark[cis] | ahhhh | 22:12 |
Hoernchen | just found one of those pretty ascii tile maps | 22:13 |
Hoernchen | alld of that was such a long time ago.. 2012 or something like that | 22:13 |
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