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| matb4[m] | <josuah> "hello matb4[m]! are you interest..." <- nothing in particular yet | 03:03 |
|---|---|---|
| matb4[m] | I need to know what to study as base to build my career | 03:03 |
| sensille | starting with fpgas with no background in technology? why fpga specifically? | 05:39 |
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| somlo | _florent_: applying PR #1736 broke my build: https://pastebin.com/yABi5dSx | 14:11 |
| tpb | Title: $ rm -rf build/digilent_nexys_video; litex-boards/litex_boards/targets/digilent_ - Pastebin.com (at pastebin.com) | 14:11 |
| _florent_ | somlo: Thanks, sorry, I'll look at it. | 14:13 |
| somlo | no worries, just doing my regular CI duties :D | 14:13 |
| _florent_ | This should be good now | 14:20 |
| somlo | yep, made it all the way to vivado this time (which is still at it, and will be for the next half hour) -- thanks for the prompt fix! | 14:28 |
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| matb4[m] | <sensille> "starting with fpgas with no..." <- personal reasons | 17:39 |
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| somlo | matb4[m]: I'd start with a good textbook on digital design (the theory behind, ultimately, what FPGAs and ASICs do) before I'd try "wrangling" FPGAs | 18:09 |
| somlo | I took a uni course, so not sure about what the best intro textbook might be, but I'd start researching *that* -- and start tinkering with FPGAs as part of working through that, or once I'm done ingesting that material | 18:10 |
| somlo | learn a bit of verilog / vhdl in the process, while at it :) | 18:12 |
| gurki | designing for asic is quite different from designing for fpga imho so you should make a pick about these | 18:27 |
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| somlo | gurki: I'd say everything down to the RTL (register-transfer logic, i.e., combinational and synchronous circuits, i.e., gates and flip-flops) is more or less reusable between FPGAs and ASICS (https://imgur.com/a/8cOU8Dr) | 20:16 |
| somlo | once you have RTL, there's a whole new world of physics and materials science if you want to make ASICS, but that's *on top of* (not *instead*) of the digital design you need to know to make fpga bitstream | 20:17 |
| gurki | somlo: your asic designs will be very, very different | 21:11 |
| gurki | https://dl.acm.org/doi/abs/10.1145/1723112.1723116 this is a nice read | 21:11 |
| tpb | Title: Intel nehalem processor core made FPGA synthesizable | Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays (at dl.acm.org) | 21:11 |
| gurki | they tried the same thing with an atom core https://dl.acm.org/doi/abs/10.1145/1508128.1508160 | 21:11 |
| gurki | anything thats remotely non-trivial will have quite different fpga and asic rtl | 21:11 |
| somlo | gurki: if you mean "I wrote this pile of verilog sources, now I'm going to make both an asic and also deploy it as fpga bitstream", I *may* be convinced; but "stuff I learned about writing RTL specification of digital circuitry that fulfills some required function" is stuff you can apply whether you target FPGA deployment or are aiming to make ASICS (except you need much *more*, *additional* knowledge of various kinds to do the latter) | 21:13 |
| gurki | you might also enjoy https://ibex-core.readthedocs.io/en/latest/03_reference/register_file.html :) | 21:13 |
| tpb | Title: Register File — Ibex Documentation 0.1.dev50+g1eb0bea.d20230804 documentation (at ibex-core.readthedocs.io) | 21:13 |
| somlo | so if someone asks "what should I learn to get into this field", the answer is "start by learning to make RTL", i.e., "digital design" as a field of study :) | 21:14 |
| gurki | somlo: i agree on the "you need to start with rtl" part, i just really, really disagree with that image you posted :P | 21:15 |
| somlo | you disagree because you assume it's the exact same source going to both fpga and asic? It may help thinking about it as optional conceptual paths taking you from a HDL spec to some form of hardware. You'll have tech mapping in both cases, at/after which the tools for making FPGA bitstream and ASICS will become wildly different, but semi-kidding, they're just "stages of a compilation pipeline" :) | 21:17 |
| somlo | and the sources you're compiling may be written with knowledge of which path you're going to take, but that's nitpicking at the level of abstraction I'm at, just trying to illustrate what the moving parts are (with emphasis on the *common* ones :) ) | 21:18 |
| gurki | if i got a dollar everytime i had this discussion ... :) | 21:18 |
| somlo | bonus points for it being sort-of off-topic for this channel in particular... :D | 21:20 |
| gurki | well id like to see litex become more asic-friendly so ... :) | 21:20 |
| somlo | according to yourself, it'd have to be a hard fork ;) | 21:21 |
| gurki | honestly, i do not know enough about litex to have an oppinion | 21:21 |
| somlo | (because if not, my drawing above should apply ;) | 21:22 |
| gurki | i happily use its glue magic for quickly setting up simulations , but i hardly looked at internals | 21:22 |
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| whitequark[cis] | gurki: "swapping a few modules" is not the same as "completely different rtl" | 21:25 |
| whitequark[cis] | of course you're not going to use the same memory blocks in ASICs and FPGAs, or the same SERDES, or even the same ROM implementation | 21:25 |
| whitequark[cis] | but you're still using, for the most part, the same synchronous logic, and a somewhat similar clock tree | 21:26 |
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