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nanoric[m] | Hello, I'm new to FPGA. Am I free to ask questions about FPGA here? | 09:14 |
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sensille | nanoric[m]: i'm not the owner of this channel but i'd say it is quiet enough that you can. there's also ##fpga which is just general fpga talk with regular newbie questions | 09:31 |
nanoric[m] | Thanks! | 09:44 |
nanoric[m] | An fpga question:... (full message at <https://catircservices.org/_matrix/media/v3/download/catircservices.org/mbrJrDYBhZWFpUIvLBHkdWfB>) | 09:48 |
sensille | nanoric[m]: have you read http://www.sunburst-design.com/papers/CummingsSNUG2008Boston_CDC.pdf? | 09:55 |
sensille | relevant here maybe up to page 10 | 09:55 |
sensille | (and it is very inconvenient to have to click on a link to see your question, i'm on the irc side) | 09:56 |
nanoric[m] | sensille: Thank you for your recommand! | 09:56 |
sensille | my question would be, how do you know it is many clocks later? | 09:57 |
nanoric[m] | Because I can wait many clocks later to read it. Read operation is not eager. | 09:58 |
nanoric[m] | For example, I have a single to control the write from clock A, and another signal to control the read from clock B. The two signals are far apart in time. | 10:02 |
nanoric[m] | * in time(eg, 10 or more clocks). | 10:03 |
sensille | nanoric[m]: it should work (3 cycles should be plenty). the document might offer more solutions | 10:28 |
sensille | 5.6.1 resembles your solution | 10:38 |
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