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| _florent_ | whitequark[cis]: sorry for the delay, I'm now also on matrix (FlorentKermarrec), thanks for your time on helping us for the bridge. | 06:44 |
|---|---|---|
| whitequark[cis] | made you an admin of the room | 06:45 |
| whitequark[cis] | admins can't demote each other so I will demote myself later once it's clear the room functions correctly | 06:45 |
| _florent_ | perfect, thanks! | 07:02 |
| sensille | so without the vhdl code my design finally works with yosys. it still does not work with diamond, but the colorlite example also doesn't work with diamond | 07:08 |
| sensille | which is still a mystery to me, because the diamond post-synthesis design works in synplify | 07:09 |
| sensille | anyway, now i have to try the converter step for the vhdl, which i really wished to avoid, because it spills tons of errors | 07:10 |
| sensille | s/synplify/modelsim | 07:17 |
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| Mario1159 | Hi, it's there a reason why the sky130a pdk in conda (https://anaconda.org/LiteX-Hub/open_pdks.sky130a/files) suddendly it's 10x bigger in size than before? | 07:22 |
| sensille | great, ******* GHDL Bug occurred ******* | 07:37 |
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| josuah | sensille: not sure what could have been causing this in https://github.com/hdl/conda-eda/commits/master so maybe it is elsewhere | 10:48 |
| josuah | wait... is anaconda keeping the package definition private? | 10:56 |
| josuah | oh right, because it does not know where the "anaconda upload" command was run from, it has no idea of where the package source repo is | 10:59 |
| josuah | and cannot link back to it | 10:59 |
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