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| josuah | Hello! Here some minor edit for the LiteX wiki: https://josuah.net/paste/6Axj6FV0vJaA8uyNVI3q/patch | 09:04 |
|---|---|---|
| josuah | quick-apply: | 09:04 |
| josuah | git clone [email protected]:enjoy-digital/litex.wiki.git | 09:04 |
| josuah | curl https://josuah.net/paste/6Axj6FV0vJaA8uyNVI3q/patch | git -C litex.wiki am - | 09:04 |
| josuah | git -C litex.wiki show --color-words | 09:04 |
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| josuah | Just caught-up on https://github.com/enjoy-digital/litex/issues/1727 this looks great! :D | 09:12 |
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| _florent_ | Thanks josuah, I'll apply. | 13:13 |
| _florent_ | sensille: For simulation with verilator, you can create a simulation target, that will be very similar to your FPGA target, but that will use PHY models and Verilator stubs. | 13:14 |
| _florent_ | sensille: you can find inspiration in https://github.com/enjoy-digital/litex/blob/master/litex/tools/litex_sim.py | 13:15 |
| _florent_ | or https://github.com/litex-hub/linux-on-litex-vexriscv/blob/master/sim.py | 13:15 |
| sensille | _florent_: i tried to use litex_sim as an inspiration, but everything is different there. i currently don't need to simulate the phys. i really just want to run the design as-is, especially because small changes in the design can break it (or make it work) | 13:17 |
| sensille | so i really only want to send the result to verilator | 13:18 |
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| sensille | doesn't seem to be so easy anyway: %Error-UNSUPPORTED: /usr/local/diamond/3.12/cae_library/simulation/verilog/ecp5u/EHXPLLL.v:1121:8: Unsupported: Verilog 1995 deassign | 17:55 |
| tnt | Yeah, I wouldn't expect sim models from lattice to go through verilator. | 18:00 |
| tnt | You either need a real verilog simulator or code up your own sim models / stubs. | 18:00 |
| sensille | trying iverilog instead | 18:01 |
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