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| sensille | okay, one problem seems to be that etherbone cannot handle the initial back-to-back packets from litescope_cli, maybe when sys_freq is too low (50MHz) | 11:01 |
|---|---|---|
| sensille | etherbone locks up after that | 11:01 |
| sensille | adding a sleep in litex_server makes litescope work again | 11:02 |
| sensille | adding a ping-pong for writes would help | 11:03 |
| sensille | or a 10ms sleep after each write | 11:11 |
| sensille | oh, or is it because the cpu is hogging the bus? | 11:58 |
| sensille | finally a bit of progress: with neorv32 i can get a small program to run, just not with vexriscv. the vexriscv core just runs up the instruction counter, fetches the instruction, but doesn't seem t execute anything. loops from 0-0x1e8 | 16:24 |
| sensille | according to litescope | 16:26 |
| sensille | https://imgur.com/oEZPQTG.png | 16:40 |
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| riktw | I got a small issue with interrupts. I want to add a second uart and a second timer to a SoC and have interrupts. I added the following ( https://pastebin.com/r8FENm3X ) to an example from the litex-boards and it builds and they got added to the SoCIRQHandler. | 19:31 |
| tpb | Title: self.extratimer = Timer() uartPhy = uart.UARTPHY( - Pastebin.com (at pastebin.com) | 19:31 |
| riktw | In the software/libbase/isr.c I added a small printf to print any irq source other then the build in uart but I can't seem to generate an interrupt. Is there anything else needed, or am I missing something in code? ( https://pastebin.com/9Apyx37a ) | 19:34 |
| tpb | Title: void isr(void){ __attribute__((unused)) unsigned int irqs; irqs = irq_pe - Pastebin.com (at pastebin.com) | 19:34 |
| riktw | I also saw that I can do self.irq.add("fjnefji", use_loc_if_exists=True) with anything for the name and it does compile? Is that the expected behavior? | 19:35 |
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