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| _florent_ | Hi, sorry for not being very present... lots of projects going on... | 08:09 |
|---|---|---|
| _florent_ | tpw_rules: For now I have a preference to keep CPU integration similar for all CPUs and integration wrapper directly in LiteX, can you explain the changes you would like to do for VexRiscv-SMP? | 08:10 |
| _florent_ | tpw_rules: We could probably improve things, but we would need to think about the best approach for all the CPUs. | 08:11 |
| _florent_ | sensille: Sorry I haven't found the time to look at your issue yet. You could indeed probably simplify the logic with write only logic to the Tx buffers. | 08:13 |
| sensille | i did that, and it seems to work fine. not fully tested yet | 08:14 |
| sensille | saves tons of resources | 08:14 |
| sensille | i might prepare some pull requests for that | 08:14 |
| _florent_ | sensille: OK great, feel free to experiment/tweak the code for your need, if you made interesting finding/improvements, happy to review/integrate | 08:15 |
| _florent_ | sensille: that's possible we could switch to this as default since I'm not sure any software code re-read the TX buffers | 08:17 |
| sensille | maybe to calculate checksums | 08:18 |
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| sensille | and maybe some CPUs implement 8 bit writes as 32 bit RMW? | 09:20 |
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| sensille | oh, and unaligned 32 bit writes | 10:22 |
| sensille | _florent_: do you know how vexrisc handles 8 bit writes? rmw or with byte lane enable? | 10:29 |
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| tpw_rules | _florent_: basically the problem is that the pythondata vexriscv smp repo needs litex to automatically generate the CPUs because litex has the routine to enumerate them. in contrast for all the other CPUs each of the pythondata repos are standalone and don't need litex | 13:12 |
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