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| cr1901 | _florent_: I don't exactly have concrete feedback to give, but I ended up using Lattice Reveal for this project. I found the setup more seamless than litescope. 1/2 | 00:28 |
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| cr1901 | It uses JTAG rather than serial to talk to the chip, and the binary format used has enough information so that you don't have to add any code to your top level module for the analyzer to be integrated. | 00:28 |
| cr1901 | A far off nice goal would be "choose signals in your design, and litescope creates a SOC on your chip without you needing to add extra code". I guess that's a benefit of the tightly coupled vendor tools :/ | 00:38 |
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| _florent_ | cr1901: This would indeed useful when the SoC is not created with LiteX, when created with LiteX, you can add a LiteScope instance with just a few lines: https://github.com/enjoy-digital/litex/wiki/Use-LiteScope-To-Debug-A-SoC#add-a-litescope-analyzer-to-your-soc | 08:54 |
| _florent_ | cr1901: And operate it over UARTBone, JTAGBone, Etherbone, PCIeBone, etc... | 08:54 |
| _florent_ | cr1901: But you'll only easily observe LiteX signals. If signals are in verilog/VHDL code or generated code, you'll still have to export them to the top of the module | 08:55 |
| _florent_ | cr1901: but I agree with you, a such tool would be nice, but for now LiteScope has been enough for my personal use-cases | 08:56 |
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