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geertu | somlo: Yeah, the python upgrade is what triggered this | 07:33 |
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keesj | Hi | 08:39 |
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Melkhior | notdavid: for Wishbone, you don't need the intermediate signals you defined ; just pass the wishbone Interface to your object and hook those to your Instance. Then this Interface can be used in add_wb_slave. You don't need the connect_to_pads (not sure what that does) | 09:55 |
Melkhior | notdavid: There's a trivial Wishbone slave in <https://github.com/rdolbeau/NuBusFPGA/blob/master/nubus-to-ztex-gateware/nubus_stat.py> | 09:59 |
Melkhior | The interface is created locally and then used directly in the FSM | 09:59 |
Melkhior | and hooked to the SoC wishbone here: <https://github.com/rdolbeau/NuBusFPGA/blob/8ecda4c1d8c872fb02e04c87b51c0b80f7d0fe0a/nubus-to-ztex-gateware/nubus_to_fpga_soc.py#L421-L422> | 09:59 |
acathla | _florent_, I have a working litex with sdram on a Papilio Pro (spartan6) board. Where should I publish that? Pull Request in litex-boards? | 12:55 |
mithro | https://github.com/enjoy-digital/litex/issues/1562 is super cool! | 15:45 |
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keesj | acathla: papilio brings back good memories | 19:15 |
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