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| DerekKozel[m] | Hey _florent_, Back in 2020 you ordered a Pluto SDR. Did you ever turn it on? | 13:21 |
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| gurki | DerekKozel[m]: if you ask a specific question ppl might be able to help ;) | 13:33 |
| DerekKozel[m] | Hi Gurki. I have some Plutos and was curious if anyone had setup LiteX with it. | 13:36 |
| DerekKozel[m] | Answering some of my own question Florent made a very basic platform file in April last year, Just with a few GPIO defined. | 13:37 |
| DerekKozel[m] | https://github.com/litex-hub/litex-boards/commits/master/litex_boards/targets/adi_plutosdr.py | 13:37 |
| DerekKozel[m] | Actually bringing up the AD9364 RF frontend would be a bunch of work (I assume), though nothing new for LiteX as there are already designs using the same RFIC | 13:38 |
| gurki | ah. i cant help with litex stuff, i just happen to own and use a pluto | 13:45 |
| gurki | i assume youre aware of https://github.com/analogdevicesinc/plutosdr-fw | 13:45 |
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| knicklicht | Hey, can someone tell me why I get timing issues when I try to build ./litex_boards/targets/colorlight_5a_75x.py --cpu-type vexriscv --with-ethernet --csr-json csr.json --build. I get the following warnings: | 14:18 |
| knicklicht | Warning: Max frequency for clock '$glbnet$crg_clkout0': 59.92 MHz (FAIL at 60.00 MHz) | 14:18 |
| knicklicht | Warning: Max frequency for clock '$glbnet$eth_clocks0_rx$TRELLIS_IO_IN': 112.76 MHz (FAIL at 125.00 MHz) | 14:18 |
| knicklicht | The closed github issues seem to indicate, that liteeth should work on ECP5 FPGAs. | 14:18 |
| sensille | knicklicht: i had better success with yosys from oss-cad-suite-20220407 | 14:20 |
| sensille | but you have to experiment with some tuning. timing closure is possible, but it also failed for me out of the box | 14:20 |
| knicklicht | Thanks, I will try the alternative version of yosys. How do I go about tuning the core? | 14:21 |
| sensille | i just tried some recommended yosys setting. not sure if i can still find them | 14:22 |
| sensille | one thing to try is "scratchpad -copy abc9.script.flow3 abc9.script; synth_ecp5 -abc9" | 14:24 |
| sensille | or just "synth_ecp5 -abc" | 14:25 |
| sensille | *abc9 | 14:25 |
| knicklicht | Okay, I will have to get familiar with yosys first. I wouldn't know where to set this | 14:25 |
| knicklicht | is it correct that I use --with-ethernet and not --with-etherbone? | 14:29 |
| sensille | depends on what you want to achieve. shouldn't have an impact on the 120mhz timing | 14:30 |
| sensille | regarding the 60mhz you might also just reduce the target to 50mhz | 14:31 |
| knicklicht | I want to run zephyr on the vexriscv | 14:32 |
| sensille | --with-ethernet means you do ip in software, to whatever extent | 14:33 |
| sensille | --with-etherbone means ethernet is handled autonomously by gateware and you only map memory regions which you can access over network | 14:34 |
| knicklicht | Okay, so for my use case --with-ethernet makes sense | 14:34 |
| sensille | i guess you can run zephyr in both variants, but i have no experience with zephyr | 14:34 |
| knicklicht | Okay, thanks that helped anyways. The oss-cad-suite build got 60.47 MHz out of the box. I now only need to figure out how to get from 97.26 Mhz to 125MHz | 14:36 |
| sensille | that's the more important part | 14:36 |
| knicklicht | Where do I set the "scratchpad synth_ecp5 -abc"? | 14:37 |
| sensille | for a test you can manually edit colorlite.ys | 14:39 |
| knicklicht | Which I can find where? Sorry, I am absolutely new to Lattice FPGAs | 14:43 |
| sensille | build/gateware/ | 14:43 |
| sensille | it is automatically generated | 14:43 |
| knicklicht | So I need to interrupt the build process right after the file is generated? If I just rebuild with the "-abc9" added, the file is just overwritten | 14:50 |
| sensille | i think after the build is done, you can go to build/gateware, change colorlite.ys and call build_colorlite.sh | 14:51 |
| sensille | knicklicht: 123.46 MHz (FAIL at 125.00 MHz). close ... | 15:04 |
| knicklicht | You are my personal hero:-) .That worked. I now have 126Mhz. The clock is at 55.96Mhz, I'll just set the clock to 50MHz | 15:04 |
| sensille | \o/ | 15:04 |
| sensille | remember that yosys uses a random seed, so results may vary from run to run | 15:05 |
| knicklicht | I saw that. Maybe I'll rerun a few times until I get 60MHz | 15:05 |
| sensille | you can pass in a seed | 15:06 |
| knicklicht | do I pass it to synth_ecp5 as well? | 15:07 |
| sensille | not sure | 15:08 |
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