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| _florent_ | sensille: When using add_ethernet, you can specify phy_cd: https://github.com/enjoy-digital/litex/blob/master/litex/soc/integration/soc.py#L1626 | 11:46 |
|---|---|---|
| _florent_ | sensille: if you are not using add_ethernet, have a look at how the clock domain renaming is done in it to see how to apply it to LiteEthMAC | 11:47 |
| _florent_ | (but that's something that should be improved) | 11:48 |
| sensille | i spent quite some time there yesterday reading the code. i think phy_cd does not do the trick, it only applies to bus width != 32. but anyway, i also found that the device has not enough resources to handle an additional interface just for debugging purposes | 11:49 |
| _florent_ | ah OK... you could eventually add a second UART + UARTBone if that's possible/convenient on your system. | 11:51 |
| sensille | i tried uartbone, but that's too slow on my system, mainly because the usb uart dongle add to much latency | 11:53 |
| sensille | although echo 1 > /sys/bus/usb-serial/devices/ttyUSB0/latency_timer improved it a lot | 11:54 |
| sensille | i now have a somewhat working dev environment. my current problem ist that i can't increase integrated_main_ram_size above 0x1000. synthesis works, but the BIOS-ram-test fails | 11:56 |
| _florent_ | sensille: strange, which FPGA board are you using? | 12:07 |
| sensille | linsn_rv901t, spartan6 | 12:07 |
| _florent_ | OK, strange. And what's the test behavior? do you only get errors for addr >= 0x1000 or even for < 0x1000? | 12:18 |
| sensille | even for the base 0x40000000. write does nothing, read gives data from an address in the middle of the ROM. like offset 7758 in ROM | 12:20 |
| sensille | even stranger, 40000004 give the next word from rom | 12:21 |
| sensille | address decoding can't be that wrong | 12:23 |
| _florent_ | hmm, can your provide the generated software/include/generated/mem.h? | 12:29 |
| sensille | dump 0x40000000 show data starting at 0x7910. mem.h: https://dpaste.org/gEv4n | 13:32 |
| tpb | Title: dpaste/gEv4n (C) (at dpaste.org) | 13:33 |
| _florent_ | sensille: OK, I don't see anything specific, do you have another board to similar test? (and see if it could be an issue with ISE?) | 13:53 |
| sensille | no other spartan6 board, only artix 7 and lattice ecp5 | 13:54 |
| sensille | i should also learn how to simulate the design and see if it works in simulation | 13:55 |
| _florent_ | Just tested litex_sim --integrated-main-ram-size=0x2000 and memtest pass fine | 13:59 |
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| sensille | maybe litescope can sched some light onto this | 21:46 |
| sensille | i read the same values with mem_read from the bios and via etherbone | 21:47 |
| sensille | and what i read is always around 0x100 from the top of the bios. when the bios shrinks, the offset changes with it | 21:49 |
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