Monday, 2022-11-28

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_florent_sensille: When using add_ethernet, you can specify phy_cd:
_florent_sensille: if you are not using add_ethernet, have a look at how the clock domain renaming is done in it to see how to apply it to LiteEthMAC11:47
_florent_(but that's something that should be improved)11:48
sensillei spent quite some time there yesterday reading the code. i think phy_cd does not do the trick, it only applies to bus width != 32. but anyway, i also found that the device has not enough resources to handle an additional interface just for debugging purposes11:49
_florent_ah OK... you could eventually add a second UART + UARTBone if that's possible/convenient on your system.11:51
sensillei tried uartbone, but that's too slow on my system, mainly because the usb uart dongle add to much latency11:53
sensillealthough echo 1 > /sys/bus/usb-serial/devices/ttyUSB0/latency_timer improved it a lot11:54
sensillei now have a somewhat working dev environment. my current problem ist that i can't increase integrated_main_ram_size above 0x1000. synthesis works, but the BIOS-ram-test fails11:56
_florent_sensille: strange, which FPGA board are you using?12:07
sensillelinsn_rv901t, spartan612:07
_florent_OK, strange. And what's the test behavior? do you only get errors for addr >= 0x1000 or even for < 0x1000?12:18
sensilleeven for the base 0x40000000. write does nothing, read gives data from an address in the middle of the ROM. like offset 7758 in ROM12:20
sensilleeven stranger, 40000004 give the next word from rom12:21
sensilleaddress decoding can't be that wrong12:23
_florent_hmm, can your provide the generated software/include/generated/mem.h?12:29
sensilledump 0x40000000 show data starting at 0x7910. mem.h:
tpbTitle: dpaste/gEv4n (C) (at
_florent_sensille: OK, I don't see anything specific, do you have another board to similar test? (and see if it could be an issue with ISE?)13:53
sensilleno other spartan6 board, only artix 7 and lattice ecp513:54
sensillei should also learn how to simulate the design and see if it works in simulation13:55
_florent_Just tested litex_sim --integrated-main-ram-size=0x2000 and memtest pass fine13:59
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sensillemaybe litescope can sched some light onto this21:46
sensillei read the same values with mem_read from the bios and via etherbone21:47
sensilleand what i read is always around 0x100 from the top of the bios. when the bios shrinks, the offset changes with it21:49
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