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| sensille | interesting. I built my soc with uartbone + crossover and tried to access it via wishbone-tool -s terminal. it somehow works, but needs minutes to print the welcome message | 16:04 |
|---|---|---|
| sensille | building wishbone-tool from source does not fix it | 16:15 |
| sensille | memory access via wishbone-tool is quick | 16:26 |
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| sensille | it turned out to be a signal quality issue: i use this china ft232rl board, very simple | 19:39 |
| sensille | they managed to even screw that up: they left vccio floating. it somehow works, but not really | 19:39 |
| sensille | results in crazy crosstalk between rx and tx | 19:40 |
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