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| keesj | Hi | 13:16 |
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| dave | I'm using a vexrisv system, with a DRAM chip. I have a DMA acquisition system that grabs data into DRAM. It is then sent via DMA to external hardware. Is there a way to disable the L2 cache for parts (eg the top half) of the DRAM? | 14:38 |
| tnt | Does your vex access those parts of DRAM ? | 14:41 |
| dave | Yes. I have code at the start and heap below that. At the moment I alloc a block from heap to be used by the DMA. But I could partition the whole DRAM area. | 14:41 |
| dave | Very impressed by the dram/dma code in Litex BTW. | 14:42 |
| dave | I also want to be able to send data from the riscv, so I want to be able to write to some block directly. | 14:42 |
| sensille | can i have etherbone in a design and still handle other udp packets by the cpu? | 16:01 |
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| sensille | this might get me somewhere: self.ethcore_etherbone.udp.crossbar.get_port() | 16:18 |
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| sensille | or LiteEthUDPStreamer() instead? | 16:44 |
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| sensille | and do i map the streams to the wishbone bus myself, or is there a ready-made adapter? | 17:11 |
| sensille | or use csrs? | 17:13 |
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| _florent_ | sensille: https://github.com/litex-hub/litex-boards/blob/master/litex_boards/targets/siglent_sds1104xe.py#L98-L145 | 18:57 |
| sensille | _florent_: thanks. so that adds an etherbone interface on port 1234 as well as a direct wishbone interface to ethmac. but can i receive packets directly through the ethmac map? | 20:43 |
| sensille | i want the board to handle a second udp port with a non-etherbone protocol, in addition to etherbone | 20:49 |
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| sensille | from what i gathered so far i can add a second udp handler with LiteEthUDPStreamer and expose the stream to the cpu | 21:07 |
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