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sensille | can i use litex with yosys and vhdl? by just adding the sources as described in the wiki it tries to call "read_vhdl" in yosys | 12:50 |
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jevinskie[m] | Do you have the ghdl yosys plugin? http://ghdl.github.io/ghdl/using/Synthesis.html | 16:28 |
tpb | Title: Synthesis — GHDL 3.0.0-dev documentation (at ghdl.github.io) | 16:28 |
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trabucayre | sensille: to include VHDL you have to use VHD2VConverter | 17:27 |
trabucayre | https://github.com/enjoy-digital/litex/blob/master/litex/build/vhd2v_converter.py | 17:27 |
trabucayre | see neorv32 : | 17:27 |
trabucayre | https://github.com/enjoy-digital/litex/blob/master/litex/soc/cores/cpu/neorv32/core.py#L98 | 17:27 |
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gurki | trabucayre: that sounds like asking for trouble :S | 17:53 |
gurki | vhdl and v are quite different in a lot of tiny details | 17:53 |
trabucayre | vhdl -> v is done automatically by this class | 18:45 |
sensille | from what i see it uses the toolchain directly if i supports mixed designs, otherwise it invokes ghdl for the conversion | 18:46 |
sensille | *it supports | 18:47 |
trabucayre | yep | 18:48 |
trabucayre | most of vendors tools are able to deal with mixed langage | 18:48 |
trabucayre | but for yosys you have to use ghdl-plugin or recent ghdl version to convert vhdl -> verilog | 18:49 |
sensille | the ghdl plugin is installed, but litex seemed to have issued the wrong command. i will try the converter module | 18:49 |
gurki | trabucayre: thats beside my point. im saying "the conversion itself is a bad idea". i can see that it just calls $thing to do the actual conversion ;) | 18:52 |
gurki | if your tool can deal with mixed my point is obv moot | 18:53 |
trabucayre | master branch needs a recent ghdl | 18:55 |
trabucayre | see https://github.com/enjoy-digital/litex/pull/1475 | 18:55 |
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TrailingEdge | Do you know of any examples where I can learn how to use the i2s core (https://github.com/enjoy-digital/litex/blob/master/litex/soc/cores/i2s.py)? Am particularly interested about the C API... | 21:30 |
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