Sunday, 2022-11-20

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sensillecan i use litex with yosys and vhdl? by just adding the sources as described in the wiki it tries to call "read_vhdl" in yosys12:50
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jevinskie[m]Do you have the ghdl yosys plugin? http://ghdl.github.io/ghdl/using/Synthesis.html16:28
tpbTitle: Synthesis — GHDL 3.0.0-dev documentation (at ghdl.github.io)16:28
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trabucayresensille: to include VHDL you have to use VHD2VConverter17:27
trabucayrehttps://github.com/enjoy-digital/litex/blob/master/litex/build/vhd2v_converter.py17:27
trabucayresee neorv32 :17:27
trabucayrehttps://github.com/enjoy-digital/litex/blob/master/litex/soc/cores/cpu/neorv32/core.py#L9817:27
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gurkitrabucayre: that sounds like asking for trouble :S17:53
gurkivhdl and v are quite different in a lot of tiny details17:53
trabucayrevhdl -> v is done automatically by this class 18:45
sensillefrom what i see it uses the toolchain directly if i supports mixed designs, otherwise it invokes ghdl for the conversion18:46
sensille*it supports18:47
trabucayreyep18:48
trabucayremost of vendors tools are able to deal with mixed langage18:48
trabucayrebut for yosys you have to use ghdl-plugin or recent ghdl version to convert vhdl -> verilog18:49
sensillethe ghdl plugin is installed, but litex seemed to have issued the wrong command. i will try the converter module18:49
gurkitrabucayre: thats beside my point. im saying "the conversion itself is a bad idea". i can see that it just calls $thing to do the actual conversion ;)18:52
gurkiif your tool can deal with mixed my point is obv moot18:53
trabucayremaster branch needs a recent ghdl 18:55
trabucayresee https://github.com/enjoy-digital/litex/pull/147518:55
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TrailingEdgeDo you know of any examples where I can learn how to use the i2s core (https://github.com/enjoy-digital/litex/blob/master/litex/soc/cores/i2s.py)? Am particularly interested about the C API...21:30
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