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| bentomo | Hello again, I'm spending some time trying to create some python based hardware. But I JUST want a peripheral, I don't want an SoC or a processor. I don't have a target platform, I just want pure verilog output so I can integrate it into something else. I want to make a configurable register array of CSRStorage elements, with I/O to hook up to | 20:15 |
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| bentomo | other peripherals, and also be able to use the AutoDoc and Module Doc libraries for auto register definition. | 20:15 |
| bentomo | When I got to the verilog.convert I couldn't figure out how to fake out the platform so I could just get top I/O. Amaranth and amaranth-soc were easy enough to just do a simple module export, but I would have to basically install litex as a python module to get the autocsr and module doc. Would this be silly/cursed to mix them? | 20:17 |
| bentomo | I've got a verilog/SV background and trying to learn, and just trying to do a simple hello world to integrate into another design. I do find it odd that there don't seem to be many examples of verilog.convert(). I'd like to get my team to use this but I need to baby-step any kind of transition to open HDLs. It feels like litex/nmigen require full | 20:20 |
| bentomo | commitments of the whole design to start using them. | 20:20 |
| bentomo | Also admittedly I'm not very smart, I did not see that the cli generate option is available. Which seems to do a similar function but maybe doesn't require the platform necessary for CSR style registers. | 21:02 |
| bentomo | I'm still learning a bunch at the same time but does litex autodoc support generating an instantiation template in pure verilog/vhdl? This would also help with adoption I think. If I can convince my team to at least let me use it I can spend time contributing stuff like that if it doesn't! Fingers crossed! | 21:08 |
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