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| mithro | People might find this project interesting -> https://github.com/google/silifuzz | 01:27 |
|---|---|---|
| tpw_rules | mithro: pm? | 01:47 |
| mithro | ? | 01:47 |
| tpw_rules | do you mind if i talk to you over private message briefly? | 01:47 |
| mithro | tpw_rules: Sure | 01:48 |
| mithro | It would probably be awesome if someone would see if it is possible to get silifuzz connected up to LiteX & Verilator based simulation.... | 01:49 |
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| nickoe | Hmm, can someone refresh me. Why don't I see my module in the sim output when I have added with as self.submodules.mymod = MyModule(platform, sys_clk_freq) ? | 20:07 |
| nickoe | If I break on Builder, and inspect my soc object I do see it listed as soc.mymod ... | 20:08 |
| nickoe | I only see TOP.sim.FemtoRV32 in the gtkwave device tree | 20:14 |
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