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| tcal | fuzziphy: I know it is possible to configure VexRiscv in ways that don't work with Rust: https://github.com/SpinalHDL/VexRiscv/issues/240 . I'm not sure how the prebuilt IMAC variant is configured. | 02:15 |
|---|---|---|
| fuzziphy | thanks! I had things working well in riscv32i, and wanted to switch to imac for an atomic heap allocator. Doing some debugging still, and I think it might be a broken linker script | 02:17 |
| tcal | I am having an issue with Verilator simulation --- I'm specifying `--trace-fst` but it doesn't seem to be propagating through --- I'm getting a `sim.vcd` generated instead. I saw some mention of a similar issue in the IRC logs from a few months ago; does anyone know if that was resolved? | 02:18 |
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| fuzziphy | yeah, it I was having a stack overflow that was only happening when compiling with the riscv32imac variant :| | 03:52 |
| fuzziphy | --============= Liftoff! ===============-- | 04:08 |
| fuzziphy | _______ | 04:08 |
| fuzziphy | |__ __| | 04:08 |
| fuzziphy | | | ___ _ __ ___ _ __ | 04:08 |
| fuzziphy | | |/ _ \ '_ \ / _ \| '__| | 04:08 |
| fuzziphy | | | __/ | | | (_) | | | 04:08 |
| fuzziphy | |_|\___|_| |_|\___/|_| | 04:08 |
| fuzziphy | Rust RISCV Kernel Booting | 04:08 |
| fuzziphy | [INFO] - Logging initialized | 04:08 |
| fuzziphy | [INFO] - Heap start: 1074835928 size: 133123624 | 04:08 |
| fuzziphy | [INFO] - Heap start: 0x4010b1d8 end: 0x48000000 | 04:08 |
| fuzziphy | [INFO] - Heap initialized | 04:08 |
| fuzziphy | [INFO] - Interrupts enabled | 04:08 |
| fuzziphy | [INFO] - Allocated 0x4010b1d8, 0x4010b1e0 | 04:08 |
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| negut | Hi | 10:57 |
| negut | is anyone work on sqrl_acorn next x 4 ? | 11:03 |
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