| *** tpb <[email protected]> has joined #litex | 00:00 | |
| *** Degi_ <[email protected]> has joined #litex | 02:08 | |
| *** Degi <[email protected]> has quit IRC (Ping timeout: 276 seconds) | 02:10 | |
| *** Degi_ is now known as Degi | 02:10 | |
| *** lexano_ <[email protected]> has joined #litex | 02:17 | |
| *** lexano_ <[email protected]> has quit IRC (Client Quit) | 02:18 | |
| _florent_ | Hi | 06:32 |
|---|---|---|
| _florent_ | thanks mithro, for some of the points listed in the link, I consider some are implicit for LiteX: Code of conduct and being respectful to each other. I found sad having to have a code of conduct in a project or having to say you have to be respectful, and I consider than anyone not doing this naturally probably has nothing to do in the LiteX community, so we'll just politely let them understand (be evasive in answer, let them | 06:36 |
| _florent_ | wait, etc...) and they'll leave. | 06:36 |
| _florent_ | jevinskie[m]: we have a vga framebuffer in the simulator in the past, but this hasn't been re-integrated (yet...): | 06:39 |
| _florent_ | https://github.com/enjoy-digital/litex/commit/e890a566a9f52cf746b3feb52861092fa0e012ea | 06:39 |
| _florent_ | this was a very simple PoC using SDL | 06:40 |
| _florent_ | imgui could be really interesting to also be able to look at/control/force internal signals during the simulation | 06:41 |
| _florent_ | ie to create an interactive simulator environment | 06:42 |
| *** FabM <[email protected]> has joined #litex | 06:48 | |
| *** lexano <[email protected]> has quit IRC (Ping timeout: 248 seconds) | 08:51 | |
| *** shorne <[email protected]> has quit IRC (Read error: Connection reset by peer) | 11:27 | |
| *** shorne <[email protected]> has joined #litex | 11:33 | |
| *** FabM <FabM!~FabM@armadeus/team/FabM> has quit IRC (Quit: Leaving) | 14:43 | |
| *** acathla <[email protected]> has joined #litex | 14:53 | |
| *** proppy[m] <proppy[m]!~proppymat@2001:470:69fc:105::cfc1> has quit IRC (Quit: You have been kicked for being idle) | 16:00 | |
| jevinskie[m] | Yeah at least with VPI it’s easy to get access to internal symbols using iterators over the modules. I think verilator would need fishing signals to the top level before compilation | 20:10 |
Generated by irclog2html.py 2.17.2 by Marius Gedminas - find it at https://mg.pov.lt/irclog2html/!