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| cr1901_ | trabucayre: I don't have the bandwidth to undertake this now, but would you accept a Linux GPIO bitbang interface into openfpgaloader? | 03:51 |
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| trabucayre | cr1901: there is already a discussion and a work to use libgpiod: maybe you can try and give your opinion? :) | 04:34 |
| trabucayre | https://github.com/trabucayre/openFPGALoader/issues/230 | 04:34 |
| cr1901 | Ack, will do hopefully today or this week, thanks | 04:35 |
| trabucayre | Thanks too! | 05:00 |
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| mithro | @trabucayre Can you remind me what the colognechip is? | 17:13 |
| tnt | whttps://colognechip.com/programmable-logic/gatemate/ ? | 17:24 |
| tpb | Title: GateMate FPGA – Cologne Chip (at colognechip.com) | 17:24 |
| jevinskie[m] | GateMate, your FPGA buddy :P https://colognechip.com/programmable-logic/gatemate/ | 17:24 |
| tnt | still waiting for their linux toolchain ... it's been "coming soon" for months ... | 17:24 |
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| Shatur | pepijndevos[m]: opened a small PR to your crate: https://github.com/pepijndevos/rust-litex-hal/pull/2 | 17:58 |
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| jevinskie[m] | Starting to think I'm nuts... `self.submodules += stream.Pipeline(self.uart.sink, self.uart.source)` works for a sim uart loopback but `self.comb += self.uart.sink.connect(self.uart.source)` doesn't echo for me. Any ideas? I'm diffing the generated netlists now. | 18:43 |
| trabucayre | tnt: using p_r with wine is working but definitely not the best way :-( | 18:45 |
| jevinskie[m] | Indeed. | 18:47 |
| trabucayre | gatemate is working with LiteX (no-cpu + no-uart, or no-cpu + uart), I have a PR for edalize too | 18:49 |
| jevinskie[m] | OK, so my issue is the order of assignments in the generated verilog. Using Pipeline `uart_uart_source_valid <= uart_uart_sink_valid` is the last assignment while using raw connect I get `uart_uart_source_valid <= uart_tx_fifo_source_valid;` as the last assignment | 18:51 |
| jevinskie[m] | https://gist.github.com/jevinskie/50382d3050af7e4282e9e1dbc6e741f4 | 18:51 |
| tnt | trabucayre: I don't have (and don't want) any 32b libs on my system ... if the vendor can't be bother to provide proper tools I'm not going to bother using their chips ... | 19:01 |
| trabucayre | Missing native pnr tools for linux is my regret... Yep | 19:04 |
| trabucayre | and emerge wine on my """old""" x230 take time... | 19:05 |
| jevinskie[m] | Bagh, if I do the connect in a stub submodule it works. What is going on with this signal assignment ordering? :( | 19:09 |
| jevinskie[m] | `class Dummy(Module): | 19:09 |
| jevinskie[m] | def __init__(self, sink, source): | 19:09 |
| jevinskie[m] | self.comb += sink.connect(source)` | 19:09 |
| jevinskie[m] | Hmm... if I force verilog generation with _print_combinatorial_logic_synth instead of _print_combinatorial_logic_sim it works... | 19:40 |
| jevinskie[m] | _florent_: any ideas? | 19:40 |
| jevinskie[m] | I forget the exact reason behind two different styles of verilog for synthesis and simulation. I know that yosys breaks up things differently for simulation for perf reasons: https://github.com/YosysHQ/yosys/pull/761 | 19:48 |
| jevinskie[m] | Nvm, I was still testing with the dummy module. the sim vs synth verilog doesn't seem to be the issue | 19:52 |
| zyp | jevinskie[m], sounds like you're trying to connect to endpoints that are already connected and seeing differing behavior depending on which connection gets emitted first in the verilog | 19:53 |
| zyp | if so; don't do that, ensure the original connection doesn't happen first | 19:54 |
| jevinskie[m] | Doh, you're right. I should just instantiate the uart phy and not use add_uart | 19:55 |
| zyp | indeed | 19:55 |
| jevinskie[m] | I wonder if this id10t error can be detected at runtime? | 19:55 |
| zyp | amaranth does error if you tried assigning the same signal from multiple modules -- one of the improvements it got over migen | 19:57 |
| zyp | (ask me how I know, I were the idiot :) | 19:58 |
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| jevinskie[m] | Thanks a bunch zyp! I wonder if a warning if there are > 2 (reset and combinatorial) assignments | 20:24 |
| jevinskie[m] | If you could emit a warning* | 20:24 |
| zyp | no, in some cases it's what you want | 20:28 |
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