Tuesday, 2022-06-28

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ShaturShould the CPU reset address point to ROM or SpiFlash?07:10
_florent_Shatur: it will depends what you are trying to do. I'm having trouble understanding what you want to achieve, so as described in the issue, sharing the big picture would help to answer :)08:54
Shatur_florent_: makes sense, answered :)08:56
Shaturin the issue*08:56
_florent_Shatur: ok thanks, just answered. But I don't think the issue is in LiteX, it's probably just some adaptation to do to the Rust example you are using (I'm not familiar with Rust, but pepijndevos[m] the author of the example is here in the channel)09:04
pepijndevos[m]Oh hello09:06
pepijndevos[m]What's going on?09:06
Shaturpepijndevos[m]: hi! I trying to run your Rust example on litex_sim, but have compilation error: section '.text.dummy' will not fit in region 'spiflash': overflowed by 18446744073675997184 bytes09:09
ShaturI regenerated svd.soc and memory.x using litex_sim with the following command: litex_sim --csr-svd=soc.svd --memory-x=memory.x --with-spi-flash09:10
ShaturAnd just replaced your files with these two from litex_sim.09:11
pepijndevos[m]I've never used litex_sim with Rust. But make sure you use a release build09:13
pepijndevos[m]But also... That's a lot of bytes...09:14
Shaturpepijndevos[m]: Yes, I tried release. I believe it because of incorrect CPU reset location.09:16
ShaturBecause if I change _stext = 0x000000; into 0x01000000 it compiles.09:17
ShaturWe se so many bytes because it's a negative number. I.e. the offset is incorrect.09:17
pepijndevos[m]Right09:18
Shaturpepijndevos[m]: So there is an issue with memory.x generation for simulator?09:19
ShaturHere is the issue wich contains a little more details: https://github.com/enjoy-digital/litex/issues/134409:19
pepijndevos[m]Maybe rust embedded channel knows09:19
Shaturpepijndevos[m]: I tried asking, people rarely use simulator for such things :(09:20
pepijndevos[m]So what's wrong with changing the reset address as florent suggested09:22
pepijndevos[m]Or putting sections in rom09:23
Shaturpepijndevos[m]: I changed it, it compiles. But is this expected? I meant shouldn't litex_sim generation point to the correct location?09:23
ShaturAlso after compilation I tried to put the generated image to rom and to sdram. It boots, but there is no output from UART (I assume it should print to console by default via serial2console module which is enabled by default).09:24
Shaturin boots in both variants (from rom rom instead of BIOSN and from sdram with BIOS from rom)09:26
ShaturThis is why I not sure if I even did it correctly.09:26
ShaturThere is no tutorials on running software on litex_sim, unfortunately.09:27
pepijndevos[m]I also override settings in my linking https://github.com/pepijndevos/rust-litex-example/blob/master/memory.x09:30
pepijndevos[m]I take regions.ld from the generated code and define where I want to keep things https://github.com/pepijndevos/rust-litex-example/blob/master/.cargo/config09:32
ShaturOh, so it's totally fine to edit it?09:34
ShaturOkay, thank you a lot! Your example is very usefull.09:34
Shaturpepijndevos[m]: Last question: what PROVIDE(UART = DefaultHandler); is doing?09:36
pepijndevos[m]I can't remember. I think it might add a dummy interrupt handler or something?09:38
ShaturWill play with it, thanks!09:44
ShaturFor some reason I don't see UART output in simulator console, and this is probably why.09:44
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ShaturShould UART data be output to the litex_sim console? I'm trying to run a simple example where I write "Hello world" to UART but I can't see anything. Is this expected?12:11
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leonsThat depends on whether you loaded the console module, but running vanilla litex_sim should do that13:25
leonsAre you sure your printing a line break at the end to flush buffers?13:25
Shaturleons: Yes, I didn't override `--serial`, so it should be loaded. Thank. Then the issue in how I write to UART...14:05
ShaturYes, I adding a newline, hm...14:05
leonsOut of curiosity, what are you trying to run? Custom bare metal or some OS / abstraction layer?14:06
leonsIf you're implementing a custom driver, perhaps this can help: https://github.com/tock/tock/blob/master/chips/litex/src/uart.rs#L10614:07
Shaturleons: Custom bare metal. I trying to print "Hello world" to console :)14:08
leonsI've spent some significant time building this implementation and ironing out bugs with edge cases, I'd say it's a fairly complex, complete and battle-tested implementation (sent Gigabytes of random, unpredictable data with variable timing & scheduling through that)14:08
Shaturleons: Thanks, will take a look! I just trying to start from something simple, I'm new to hardware / fpga.14:11
leonsShatur: sure, makes sense. While the LiteUART seems rather simple at first, I found the register API to be a little unergonomic when it comes to edge cases. Perhaps the implementation can give you some hints.14:12
Shaturleons: made it work with simple naive implementation, thank you!14:23
leonsCool. What was the issue?14:23
Shaturleons: I tried the implementation from this repo first and it didn't worked for some reason: https://github.com/icebreaker-fpga/icebreaker-litex-examples/blob/master/r-riscv-blink/src/print.rs14:25
ShaturBut then I tried this implementation and it just works: https://github.com/pepijndevos/rust-litex-hal/blob/master/src/lib.rs14:26
ShaturBut I think it worth using what you linked. Is it available on crates?14:27
leonsShatur: No, I think it's rather tightly coupled with other parts of the Tock ecosystem, e.g. the register abstraction and UART HIL14:28
Shaturleons: oh, I see. Probably will try to write something simillar using the link you provided as a reference.14:29
ShaturFinally I have something working :) Because before I even wasn't sure if it was loaded correctly.14:29
leonsShatur: I know the feeling. Congrats!14:29
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jevinskie[m]trabucayre: I've been thinking about integrating other simulators into litex and was wondering if your generic_toolchain work would touch on that or ease it? I did something a while ago to get LiteX simulations working with cocotb and iverilog but it was kinda hacky. I'd like to get plain iverilog support, then cocotb integration, and maybe finally questa for some perf improvements over iverilog.15:10
trabucayrejevinskie[m]: I haven't currently managed to check verilator.py but code seems have a structure quite equivalent to GenericPlatform so I assume it may possible to do something15:17
trabucayres/GenericPlatform/GenericToolchain/g15:19
trabucayreI don't know if adding sim aspect in GenericToolchain is the good way due to complexity15:22
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trabucayremaybe a GenericSimToolchain with the same philosophy15:22
jevinskie[m]Ok! Looking back at it it really wasn't bad, looks like it was less than 200 lines for the Toolchain class plus the cocotb<>migen RPyc magic and the pydev magic (needed for debugging under PyCharm, that was infuriating to figure out). https://github.com/jevinskie/litex/blob/jev/main/litex/build/sim/cocotb.py#L13215:22
jevinskie[m]One of the limitations of verilator is lack of support for delayed statements so most vendor provided models won't work.15:28
trabucayrejevinskie[m]: sorry day job meeting :-(17:10
trabucayreyour code is not really big so I'm not sure using a generic approach is really relevant17:11
trabucayreFor toolchain it's make more sense, and I think to another round of refactoring.17:12
jevinskie[m]No problem!17:28
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jevinskie[m]I’m not keen on redoing all of the modules in VPI or adding an abstraction layer. Maybe I can emulate the verilator interface with VPI? 😬22:41
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