Sunday, 2022-05-22

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shorne_swetland: I find understanding qemu command line arguments more difficult then the actual code for developing new hardware in qemu12:36
geertushorne_: +112:38
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jevinskie[m]_florent_: I’m adding altera unique chip ID and ADC support to litex. Would you like me to put them in and or create new platform generic and
_florent_jevinskie[m]: nice, you can use generic names yes. Later we could convert to a directory and move more ADC in it.17:27
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swetlandshorne_: absolutely.  the C code is much more navigable18:50
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HammdistI'm trying to generate the liteeth MAC for versa 5g in wishbone mode. the generated module has only an output wire interrupt, not a complete wishbone attachment interface. did I miss an important step?20:04
Hammdistwell I tried with exactly this config: and I get the same results (no wishbone on the module). might be some kind of regression?20:10
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Hammdist8733aecf89d56e1215dedd491bcd8fdea3fb21d9 is the first bad commit20:38
Hammdistwell if I git revert that commit relative to master it seems to work20:47
Hammdistso where can I find a sample driver for the wishbone interface?21:20
Hammdistfound something that might be helpful for me though I'm not proficient in rust at all:
tpbTitle: - source (at

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