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| jevinskie[m] | Anybody have a litex/migen wishbone to Avalon-mm bridge? Mine seems to lock up the csr and main CPU right now. https://github.com/jevinskie/litex/blob/5a48ef54477bdecc6a04d7ba6154d6ca5ad50b30/litex/soc/interconnect/avalon.py#L87 (locking-up line commented out:) https://github.com/jevinskie/pcie-mitm/blob/6d0fb4b90e0e7e5685e46c4911f84245a03a076a/test/avalon_mm_gpio/arria_v_hpc.py#L101 | 07:30 |
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| jevinskie[m] | Once I get this Avalon-MM PIO bridge working I’ll add DDR3 support to DECA using the Altera External Memory IF IP :) | 07:32 |
| _florent_ | jevinskie[m]: For traceability, I've been working several years on avionics certification in my early carrier (10 years ago) and I'm currently discussing with previous colleagues that seems interested by tools similar to LiteX but that would requires a new HDL generation to matches their needs (and source to source traceability is one of the requirement). So while revisiting the HDL generation, I'll also try to make sure it can | 08:19 |
| _florent_ | be used for these purposes. | 08:19 |
| _florent_ | jevinskie[m]: I've probably used Avalon-MM in the past, but not sure I remember much. Happy to have a closer look with you if you are stuck. | 08:21 |
| shorne | _florent_: I think it should not take too long to bisect. I will let you know if it needs reverting. | 11:18 |
| _florent_ | For those interested in CPU design, Dolu1990 (VexRiscv) is working on a new CPU with very nice specs, already able to boot Linux: https://github.com/SpinalHDL/NaxRiscv | 13:04 |
| geertu | _florent_: Thx for the link! Do if you if there are any small linux-capable RV64 cores under development? | 13:16 |
| _florent_ | geertu: I know Dolu1990 has plans for this but first wanted to have a clean new implementation, so I think that's the long term plan for Nax :) | 13:19 |
| _florent_ | geertu: BTW, Nax should also be available in LiteX soon | 13:20 |
| geertu | _florent_: Good! Looking forward to giving it a try. | 13:27 |
| DerekKozel[m] | Coming up in a bit under two hours: https://fosdem.org/2022/schedule/event/radio_julia_litex/ | 13:35 |
| tpb | Title: FOSDEM 2022 - P2P SDR to GPU Streaming with Julia and LiteX (at fosdem.org) | 13:35 |
| _florent_ | DerekKozel[m]: thanks, the project is available here BTW: https://github.com/enjoy-digital/xtrx_julia | 13:38 |
| DerekKozel[m] | I have my XTRXs out and hope to try it here soon | 13:39 |
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| sajattack[m] | happy february. any news on the acorn baseboard? | 19:58 |
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| jevinskie[m] | _florent_: thanks for the offer for help! I'll keep hacking on it and if I can't make progress I'll share a reproducible setup for the DECA (a handy lingua franca like the arty it seems). | 21:39 |
| jevinskie[m] | I tried out the "smart base selection" for verilog literals and it seems to work well with bus-related literals. See here for an example: https://gist.github.com/jevinskie/f506c9b05a3aff3e8c77fb21d4406615/revisions | 21:40 |
| jevinskie[m] | And the ugly heuristics to do it: https://github.com/jevinskie/litex/commit/9b5c56051b998aff8c19a8286c285feb28dd1fae | 21:41 |
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