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MoeIcenowy | oops GW1NR-9C QN88P PSRAM has two chips | 18:35 |
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MoeIcenowy | and their port definition just doubles the width of one port | 18:36 |
MoeIcenowy | (the PSRAM is in fact HyperRAM too and can be driven with litehyperbus | 18:36 |
MoeIcenowy | weird, what should I do... | 18:36 |
MoeIcenowy | well a top design port can only be requested once, but I can then slice it... | 19:21 |
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_florent_ | MoeIcenowy: I started the HyperRAM port on the 4K, it was compiling correctly but not working yet, I haven't investigated yet | 20:38 |
_florent_ | this should be a bit similar on the 9K | 20:38 |
_florent_ | https://github.com/litex-hub/litex-boards/blob/master/litex_boards/platforms/sipeed_tang_nano_4k.py#L54-L60 | 20:38 |
_florent_ | https://github.com/litex-hub/litex-boards/blob/master/litex_boards/targets/sipeed_tang_nano_4k.py#L105-L119 | 20:39 |
_florent_ | here is a blog post where they got it working: https://justanotherelectronicsblog.com/?p=986 | 20:42 |
tpb | Title: Sipeed Tang 4K ramblings - jaeblog jaeblog (at justanotherelectronicsblog.com) | 20:42 |
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