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| thirtythreeforty | Migen question: I need some unique identifier for the clock domain that a module will end up being clocked by. How should I do this? Things I've tried: | 01:34 |
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| thirtythreeforty | - Ask the module to keep hold of it as self.clk or whatever. This does not work because strings like 'sys' are not unique until .finalize() is finished. | 01:35 |
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| thirtythreeforty | (and in fact 'sys' might get renamed for a variety of reasons, so...) | 01:35 |
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| thirtythreeforty | - Have a ClockSignal() in the module in question. ClockSignal's self.clk *will* be updated by the visitor when ClockDomainsRenamer walks the tree. This is better, because now I can get the real clock domain from the module after .finalize() | 01:37 |
| thirtythreeforty | but, this still doesn't work because eventually the module doing the walking (via xdir()) must also be a submodule, and *its siblings* will not be finalized by the time the walker's do_finalize() is running, so the same caveat about 'sys' not being the real clock domain still applies | 01:38 |
| thirtythreeforty | So, what to do? The ultimate goal is to learn which clock each module is using so I can connect it to the appropriately-clocked bus | 01:39 |
| thirtythreeforty | (Also, is this easier in nMigen?) | 01:43 |
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| _florent_ | thirtythreeforty: I'm not sure to understand correctly your question, but for this, I would probably do the opposite: Have a clock domain in the submodule, expose it and clock the logic with this clock domain. Then at the top, connect the clocks of each submodule. In fact in a way very similar to traditional (S) Verilog/VHDL designs. | 06:30 |
| _florent_ | thirtythreeforty: if this is not answering your question, can you create an issue in LiteX to discuss this and share minimal code of what you are trying to do? | 06:31 |
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| paultech | Looks like nMigen is now called Amaranth? Seems to have broken a few things:( | 14:44 |
| tnt | _florent_: https://pastebin.com/MVUa3jCx | 14:47 |
| tpb | Title: Creating Serdes0Measuring Serdes0 frequencies...TX freq: 153.903MHzRX f - Pastebin.com (at pastebin.com) | 14:47 |
| tnt | paultech: :/ I hate name changes | 14:48 |
| tnt | _florent_: so that looks like good news ? | 14:49 |
| paultech | Yeah this one seems fairly intrusive. Changed repo URL, changed default branch, changed folder structure | 14:50 |
| tnt | _florent_: Or possibly not ... works even without --loopback which it should definitely not ... | 14:50 |
| paultech | Should litex_setup support different branches? Seems to be master only atm | 14:50 |
| paultech | Took all of 10 seconds. clone="recursive",branch="main") but unsure if breaking some convention if everything else uses master | 14:54 |
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| paultech | Python package is also amaranth-yosys now, broke ci. How rude | 15:19 |
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| tnt | So looks like the "tx freq is at 122.88" (the measured one in the pastebin above is bad because of measurement imprecision since litex_server is remote though vpn and forwarded ports etc ...). | 15:35 |
| tnt | and the rx freq is actually 0 ... | 15:35 |
| tnt | So that's obviously not good. | 15:35 |
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| tnt | Any clue how to debug ? | 15:57 |
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| whitequark | hey folks, I know the nMigen to Amaranth name change was going to break a few things | 16:26 |
| whitequark | I'd be happy to assist in fixing the breakage | 16:28 |
| cr1901 | cc: paultech, I posted the log into #amaranth-lang with your msgs highlighted. I have no idea why CI broke | 16:34 |
| cr1901 | but I have some symlinks and program settings that depend on the old nmigen name, and I'd rather wait to break those settings until litex has handled the name change | 16:35 |
| paultech | cr1901, whitequark, Don't think anything is broken on litex side yet. The setup script broke due to lack of a master branch but since remaining packages are still available I believe litex CI will build (apart from the previously mentioned failure with the setup script) | 16:39 |
| paultech | Will leave that to _florent_to test out | 16:39 |
| _florent_ | Hi whitequark, thanks for letting us know, nice new name! The breakage should be limited and easy to fix for LiteX. I'll have a closer look in the next days. | 17:01 |
| _florent_ | tnt: the first thing to look at is the TX/RX initialization, the TX/RX freqs | 17:04 |
| _florent_ | tnt: so maybe you could add LiteScope and verify the TX/RX initialization FSM | 17:04 |
| tnt | The TX freq looks fine. RX freq is zero. rx_ready stays at 0. I'm digging into the RX init fsm right now. | 17:06 |
| tnt | I've never used litescope actually, no idea how that works. | 17:06 |
| _florent_ | it's very easy to add it to your design: https://github.com/enjoy-digital/litex/wiki/Use-LiteScope-To-Debug-A-SoC#add-a-litescope-analyzer-to-your-soc | 17:20 |
| _florent_ | and since you probably already have a UARTBone bridge in your design, it will be even easier | 17:20 |
| _florent_ | Just add the analyzer | 17:20 |
| tnt | Why is litescope repo a github template ? | 17:21 |
| _florent_ | and you can use litescope_cli over the same litex_server that you are currently using for test_prbs.py | 17:21 |
| tnt | Thanks for the howto, got it added with a few signals related to rx init status. | 17:21 |
| tnt | (easy indeed, nice :) | 17:22 |
| whitequark | https://github.com/enjoy-digital/litex/pull/1130 | 17:22 |
| _florent_ | litescope repo a github template ? Sorry, not sure to understand | 17:22 |
| tnt | Go to https://github.com/enjoy-digital/litescope | 17:22 |
| tnt | https://i.imgur.com/TDobCaK.png | 17:22 |
| tnt | It says "public template" and "Use this template" instead of the normal clone button. | 17:23 |
| _florent_ | whitequark: Thanks! | 17:24 |
| _florent_ | tnt: Thanks, this is fixed (LiteScope public template) | 17:31 |
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| tnt | Looks like RXRESETDONE never comes up. | 18:16 |
| tnt | There is a RX clock ( RXOUTCLK ), it's just that because the init never finishes, it stays in reset. | 18:45 |
| MoeIcenowy | how could I connect a FPGA's internal flash (co-packaged SPI Flash, accessible as a blackbox HDL module) to LiteSPI? | 19:10 |
| MoeIcenowy | how should I construct the pads needed by LiteSPIPHY, make them connect to a Instance of the blackbox HDL | 19:11 |
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| MoeIcenowy | I now created a Record and use them as the signals connected to the Instance and pass it as pads to LiteSPIPHY | 19:11 |
| tnt | _florent_: mmm ... looks like the 1ms timeout in the init time machine was too short, it just kept resetting before it was done going through its internal init. | 19:19 |
| tnt | Looking at the wait timer value, it seems to have taken ever so slightly above 2 ms. | 19:20 |
| tnt | And now if I have the loopback disabled, I have tons of errors (kind of expected) and if it's enabled, no errors. | 19:22 |
| MoeIcenowy | https://paste.aosc.io/paste/Rk3AbVJ0I0By9W1YKhbsPw my current try to connect LiteSPI flash to the blackbox | 19:38 |
| tpb | Title: Pastebin | AOSC Pastebin (at paste.aosc.io) | 19:38 |
| tnt | MoeIcenowy: and that doesn't work ? | 19:47 |
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| MoeIcenowy | tnt: that does not work... | 19:56 |
| MoeIcenowy | things do not get connected | 19:56 |
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| tnt | MoeIcenowy: did you look at the verilog output see what it did ? | 20:11 |
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| _florent_ | tnt: Great, init time is indeed different between type of transceiver, result of test_prbs seems good | 21:10 |
| tnt | _florent_: I currently don't have an external loopback to test with, maybe next week. | 21:15 |
| tnt | I checked the talisse adi chip doesn't have any loopback mode I can enable, but it does have a PRBS mode I can try. | 21:15 |
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| shorne_ | _florent_: I got the package, thank you | 23:04 |
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