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| tnt | What would be the "canonical" way of creating a GPIO block with only a subset of the subsignals of a resource ? | 12:23 |
|---|---|---|
| tnt | Mmm ... even the full resource doesn't work. Am I missing something obvious here ? | 13:47 |
| _florent_ | tnt: you could do something like this | 13:48 |
| _florent_ | https://www.irccloud.com/pastebin/1WXPBT3I/ | 13:48 |
| tpb | Title: Snippet | IRCCloud (at www.irccloud.com) | 13:48 |
| _florent_ | If this is not covering what you want to do, can you share a bit more info? | 13:48 |
| tnt | That doesn't work with GPIOTristate. | 13:50 |
| tnt | https://pastebin.com/UjeMbWHQ | 13:50 |
| tpb | Title: ("adrv9009_ctl", 1, Subsignal("reset_n", Pins("AH18")), - Pastebin.com (at pastebin.com) | 13:50 |
| tnt | This is what I defined. (previously I had them all in one resource, but I split them now since that seemed easier). | 13:51 |
| tnt | Really ATM all I needs are the ctl signals and they're outputs, but I'd like to be able to tristate them. (No need for input) and AFAICT I need GPIOTristate for that. | 13:52 |
| tnt | So I just tried : setattr(self.submodules, f'adrv{i:d}_ctl', GPIOTristate(platform.request("adrv9009_ctl", i))) | 13:53 |
| tnt | (setattr because it's in a loop). | 13:53 |
| tnt | (If I use the same syntax and GPIOOut, that works, so it's a bit counter-intuitive that just replacing 'Out' with 'Tristate' dosn't work) | 13:58 |
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| _florent_ | tnt: can you try this? https://github.com/enjoy-digital/litex/pull/1117 | 14:33 |
| _florent_ | (I just tested verilog generation but not compilation) | 14:34 |
| tnt | _florent_: Thanks. Yeah, at least it builds and the verilog looks correct here as well. | 14:37 |
| tnt | Arf nm ... ERROR: [Synth 8-2715] syntax error | 14:39 |
| _florent_ | ok, I look at this | 14:41 |
| tnt | assign {adrv9009_ctl0_rx2_enable, adrv9009_ctl0_rx1_enable, adrv9009_ctl0_tx2_enable, adrv9009_ctl0_tx1_enable, adrv9009_ctl0_test, adrv9009_ctl0_reset_n}[0] = main_gpiotristate0_tstriple0_oe ? main_gpiotristate0_tstriple0_o : 1'bz; | 14:42 |
| tnt | I thought that was valid TBH but apparently {} can't be a LHS. | 14:42 |
| _florent_ | tnt: I also have doubts on this when looking at the verilog :) | 14:43 |
| tnt | or rather it's the {...}[] that it doesn't like. | 14:45 |
| _florent_ | tnt: I no longer have the syntax error with https://github.com/enjoy-digital/litex/pull/1117/commits/16a43e983ed32e140bd19ab3263bc1161c610460 | 14:49 |
| tnt | _florent_: indeed, verilog looks much more sane :) | 14:51 |
| tnt | and synth passed. | 14:53 |
| _florent_ | ok good | 14:53 |
| tnt | Tx. | 14:53 |
| _florent_ | I'll merge it then | 14:53 |
| tnt | I'm not sure if it's the "right way" to expose those signals in a single resource or if I'm supposed to set them as independent signals ? | 14:53 |
| tnt | (Trying to fit the litex way of doing things). | 14:54 |
| _florent_ | I generally also put them in a single resource (but without the tristate) | 14:54 |
| _florent_ | tnt: here is an example for the LiteJESD204B integration: https://gist.github.com/enjoy-digital/cd9ea52fafaebe016e739a90983eb237 This is not a full example but should help you doing the integration. | 15:06 |
| tnt | _florent_: Oh, very nice. I'll dig into that tomorrow. | 15:08 |
| tnt | I had seen some code from artiq on m-labs but it seems based on some old version of the jesd core. | 15:08 |
| _florent_ | yes it's not up to date was also only TX, not for SDR. The one I just shared is up to date and TX + RX and used on a SDR system. | 15:10 |
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| tnt | Mmmm, Am I blind ? Where's the driver code for the SPIMaster() core ? | 19:31 |
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| tnt | nm, looks like you just write to the CSR directly, no wrapper provided. | 19:43 |
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| futarisIRCcloud | https://digilent.com/shop/arty-a7-artix-7-fpga-development-board/ | 19:48 |
| tpb | Title: Artix-7 FPGA Development Board - Digilent Arty A7 - Xilinx (at digilent.com) | 19:48 |
| futarisIRCcloud | https://twitter.com/ElectronicsbyJH/status/1465726677384933381 | 19:48 |
| futarisIRCcloud | Shame that the shipping to Australia is just as much as the board | 19:53 |
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| bjonnh | $30 more for the USB cable :D | 20:35 |
| bjonnh | I may just order that one, I'm still waiting on my ULX3S | 20:35 |
| bjonnh | Is it complicated to deal with that ARM on the Zynq-7000? | 20:39 |
| bjonnh | lets say I just want to do FPGA for now, but may be happy to have some Arm later | 20:39 |
| tnt | with jtag you can configure the fpga and completely ignore the ARM part. | 20:40 |
| bjonnh | neat | 20:40 |
| tnt | (that's what I'm doing now on a UltraScale+ Zynq :) | 20:41 |
| bjonnh | I'll need to find a Jtag cable, they sell them for the same price as the board :D | 20:42 |
| trabucayre | cable is onboard | 20:42 |
| trabucayre | you have just fo find an usb cable :) | 20:42 |
| bjonnh | <3 | 20:42 |
| trabucayre | JTAG interface is onboard | 20:42 |
| trabucayre | FT2232 (one interface for JTAG, second for UART) | 20:44 |
| bjonnh | "Briefly describe the reasons you chose Digilent for your purchase today." "Because your board works with Opensource toolchains #litex" | 20:47 |
| bjonnh | I'm sure they will be happy about that | 20:48 |
| trabucayre | you can you use linux (on PS side) to communicate with the LiteX gateware into PL too | 20:53 |
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| bjonnh | My experience with FPGAs stopped at making leds blink on a Fomu, so I'll go slowly :D | 20:56 |
| trabucayre | try to communicate with LedChaser :) | 20:56 |
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| jeffdi | Hello - I’m trying to build a version of the VexRiscv min+debug core with a small amount of cache (e.g. 64 bytes). I’ve installed scala and sbt on a Mac via Brew, but getting errors running the make targets in pythondata-cpu-vexriscv. any suggestions? | 22:02 |
| jeffdi | (venv) jeffs-mbp:verilog jeffdi$ make VexRiscv_MinDebug_Cache.v | 22:02 |
| jeffdi | sbt compile "runMain vexriscv.GenCoreDefault -d --iCacheSize 64 --dCacheSize 0 --mulDiv false --singleCycleShift false --singleCycleMulDiv false --bypass false --prediction none --outputFile VexRiscv_MinDebug_Cache" | 22:02 |
| jeffdi | WARNING: A terminally deprecated method in java.lang.System has been called | 22:02 |
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| zyp | that warning looks like it can be ignored, which errors are you getting? | 22:04 |
| mithro | I ordered 20 of the Digilent Arty A7 35T boards :-) | 22:05 |
| mithro | jeffdi: Can you provide a link to the complete output? | 22:05 |
| bjonnh | mithro: are you stockpiling ? | 22:06 |
| mithro | tcal: Has a lot of experience with sbt and LiteX thanks to his work on the CFU playgournd (http://cfu-playground.rtfd.io/) | 22:06 |
| mithro | bjonnh: I send them out to people who contribute to my projects | 22:06 |
| tcal | jeffdi: yes, especially the first time you run the build, there are lots of warning that can be ignored. I don't recall seeing that one...I recall ones about duplicate main methods. | 22:06 |
| jeffdi | tcal: reposting using gist. not sure what else to provide https://gist.github.com/jeffdi/8dbc17a777492bff039951985a803c0f | 22:17 |
| tcal | jeffdi: is the ./ext/VexRiscv/ submodule loaded? What do you see in that directory? | 22:22 |
| jeffdi | tcal: just posted the output from find ext -print | 22:29 |
| tcal | In the verilog/ directory with the `Makefile` that you're using, there should be an ext/ directory, and VexRiscv inside that, unless things are completely different with mac development. | 22:30 |
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| jeffdi | tcal: yes, there is | 22:32 |
| tcal | jeffdi: FYI if we can't get to the bottom of this before I need to run, try asking at https://gitter.im/SpinalHDL/VexRiscv (you can log in with your github credentials) . @Dolu1990 is the creator of VexRiscv. | 22:34 |
| tpb | Title: SpinalHDL/VexRiscv - Gitter (at gitter.im) | 22:34 |
| tcal | jeffdi: What's inside the directory? Something like this? | 22:35 |
| tcal | https://www.irccloud.com/pastebin/KjjeO759/ | 22:35 |
| tpb | Title: Snippet | IRCCloud (at www.irccloud.com) | 22:35 |
| bjonnh | mithro: great so that's an even better discount than the digilent one! | 22:37 |
| tcal | jeffdi: dolu1990 is in Europe so you probably won't get a reply until tomorrow. | 22:51 |
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| cr1901 | Is Dolu1990 on the slack side of the bridge? | 22:53 |
| cr1901 | Wait, wrong channel lol | 22:54 |
| jeffdi | tcal: this is what i see https://gist.github.com/jeffdi/8dbc17a777492bff039951985a803c0f#file-find-ext-print | 22:55 |
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| tcal | Oh, that might be your issue. Run `git submodule`. Also, `cd` into `ext/VexRiscv` and run `git remote -v`. If the submodule is loaded correctly, for the latter command, you'll see: | 23:09 |
| tcal | https://www.irccloud.com/pastebin/11JJBUEx/ | 23:09 |
| tpb | Title: Snippet | IRCCloud (at www.irccloud.com) | 23:09 |
| tcal | jeffdi: If the submodule is not loaded correctly, then first you have to recursively delete `target/` in `ext/VexRiscv`, and then run `git submodule update --init --recursive` while sitting in the `verilog/` directory above. | 23:11 |
| jeffdi | tcal: thank you!! i think that did it! its running now... | 23:15 |
| tcal | 👍 | 23:23 |
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