Friday, 2021-11-26

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AleksaHi all! I'm trying to fit my FPGA design into a smaller part by swapping out a MIG generated DDR3 controller with the litedram core. I've generated it standalone (to stay inside vivado for now) using I noticed it came with a wishbone bus, I left it disconnected when I swapped the core in for the MIG controller and it doesn't seem to work at01:58
Aleksaall. Is there any way this core can work off the bat like the MIG, or will I have to talk to it before it starts working?01:58
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_florent_Aleksa: You can generate a core very similar to MIG (with CPU/firmware) integrated for the calibration. That's what will do litedram_gen arty.yml for example06:23
_florent_You can then customize the type of CPU (I generally use VexRiscv Min variant for this)06:23
_florent_and the user ports06:24
_florent_the calibration will be done automatically and reported on init_done /init_error outputs06:24
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ejcspii_florent_ Hi Florent, this is the addition to
tpbTitle: WB test - (at
_florent_ejcspii: Thanks, it is also possible to share wb_test_slave.v? I could then test it myself07:49
ejcspii_florent_ Here it is:
tpbTitle: module wb_test_slave( input wire i_clk, i_re - (at
ejcspiiNever tried to do wishbone before. Thanks in advance!07:54
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_florent_ejcspii: I was able to reproduce the issue with litex_sim08:07
_florent_ejcspii: and did a quick fix on the wb_ack in wb_test_slave.v08:07
tpbTitle: Snippet | IRCCloud (at
AndrewD_florent_: did you get the email about meeting to discuss collaboration?08:07
_florent_AndrewD: Ah sorry, got it but forgot to answer after reading it.08:09
ejcspii_florent_ Thank you, so I should not just ignore wb_cyc.08:11
ejcspiiAnd thanks for the diff, I'll look into the simulation myself.08:13
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AleksaFlorent: Thanks for the clarification! I set CPU to none, thinking it had to do with the rest of litex, but I now see that it's a very small CPU dedicated to calibrating the DDR3 controller. Can't wait to get it working tonight, between the low logic usage and the much faster compile time, the litedram core makes me never want to use MIG again lol14:28
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tntSo I used to include base/uart.h to get UART_EV_RX ... now that header seem gone and I don't see where to get that #define from.15:02
tntnm ... 15:04
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tntNext step is figure out how to unbreak the firmware build ... :/  I don't want any of the picolibc, I have all my own stuff.15:15
tntHow do I disable the quiet build ?  ( like instead of "CC       firmware.elf"  I want the full thing it's trying to do)15:17
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cr1901tnt: It's in the top-level Makefile how to disable the quiet build. If I remembered the exact invocation, I would tell you :P15:29
cr1901Set V=1, presumably in the environment so GNU Make knows to steal that value for its own variables15:30
tntcr1901: yup tx, works.15:32
tntLooks like a bunch of my issues aren't actually litex but tinyusb having changed some stuff.15:33
cr1901tinyusb himself appears to have vanished15:33
cr1901His Twitter acct is gone, and my last email to him went unanswered15:33
tntWell there was a commit 4 days ago.15:34
cr1901Oh? Hmmm...15:34
cr1901Ohhh whoops15:35
cr1901It's too early in the morning15:35
cr1901Ignore my comment- tinyusb* is pretty good at getting back to ppl.15:35
tntOh yeah Luke Valenty is gone from OSS/Public stuff 15:35
cr1901Which is his prerogative, but I wish he at least notified ppl/xferred ownership of some repos.15:36
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tnt:/ Seem the picolibc stuff is hardcoded I don't easily disable it.15:49
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cr1901No, and the picolibc stuff was one reason I wanted to port all of litex to meson- so everything could be under a single ninja file15:50
tntI have my own printf and stuff like that, I don't want any of theirs :/15:51
cr1901(ninja is not GNU makeserver-compat either, so a top-level make will spawn "ncores" make instances and "ncores + 2" ninja instances15:51
cr1901I'm pretty sure there was a commit recently to skip building picolibc tho15:52
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