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| cr1901 | Does anyone have a "known good" example of an icebreaker SoC made with litex? | 06:06 |
|---|---|---|
| cr1901 | I can't seem to get the software/bios part of mine to work ._. | 06:06 |
| tnt | cr1901: https://github.com/no2fpga/no2migen/blob/master/examples/1bitsquared_icebreaker_usb.py is the most recent I have. | 06:13 |
| _florent_ | cr1901: I'm regularly using this: python3 -m litex_boards.targets.1bitsquared_icebreaker --cpu-type=serv --build --flash | 06:13 |
| cr1901 | I'll try those later, thanks | 06:14 |
| _florent_ | DerekKozel[m]: The checkout in litex_setup is fixed with https://github.com/enjoy-digital/litex/commit/f92a185109f1bb9d9ae52cc2b588628818d249af | 06:43 |
| _florent_ | DerekKozel[m]: And Meson install/version is now checked with https://github.com/enjoy-digital/litex/commit/2a109c3a3ee1d765f6c8da7f637d76f2f10e9af7 | 06:43 |
| _florent_ | This would be good to have this directly checked in picolibc but for now this will reduce the support in LiteX for this specific point :) | 06:47 |
| DerekKozel[m] | Thanks! | 06:51 |
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| mntmn | interesting, with quadcore vexriscv, /sbin/init hangs | 13:40 |
| DerekKozel[m] | _florent_: Should CSR_ICAP_SEND_ADDR be CSR_ICAP_WRITE_ADDR? | 14:07 |
| DerekKozel[m] | https://github.com/enjoy-digital/litepcie/blob/fbfd1e740e20cae3777c9b1f9822cecb2d6c59b8/litepcie/software/kernel/main.c#L725 | 14:07 |
| DerekKozel[m] | /home/dkozel/src/litex/build/sqrl_acorn/driver/kernel/main.c:725:40: error: ‘CSR_ICAP_SEND_ADDR’ undeclared (first use in this function); did you mean ‘CSR_ICAP_READ_ADDR’? | 14:07 |
| DerekKozel[m] | 725 | litepcie_writel(chan->litepcie_dev, CSR_ICAP_SEND_ADDR, 1); | 14:07 |
| DerekKozel[m] | Searching through history I can't find SEND_ADDR elsewhere | 14:09 |
| _florent_ | DerekKozel[m]: I indeed added READ capability to ICAP recently and then renamed the send CSR to write. | 14:30 |
| _florent_ | DerekKozel[m]: I just updated LitePCIe with https://github.com/enjoy-digital/litepcie/commit/2d6830fff324aa6a03c94c2258f2f15268038082, thanks for the feedback (it seems there are still things missing in the CI :)) | 14:31 |
| DerekKozel[m] | Thanks! | 14:32 |
| DerekKozel[m] | Happy to be a manual CI here | 14:32 |
| DerekKozel[m] | The GNU Radio -> PCIe Loopback -> GNU Radio setup is working well for data transfer now. I'm working on automating the build and load of the FPGA now | 14:33 |
| DerekKozel[m] | Do you have any handy examples of code using the ICAP read/write? | 14:34 |
| DerekKozel[m] | Currently I'm using the OpenOCD functions | 14:35 |
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| mntmn | what's the right way to define pads as GPIOs that can be toggled from linux (userspace)? | 14:43 |
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| mntmn | _florent_: i need some GPIO outputs. is there any magic i have to do to get them to show up in the dts other than name the submodule "leds"? | 15:16 |
| mntmn | so far i did: | 15:16 |
| mntmn | self.submodules.leds = GPIOOut(platform.request_all("gpio")) | 15:16 |
| mntmn | self.add_csr("leds") | 15:16 |
| mntmn | ah, i see they actually show up in the DTS now, just with status = "disabled"; | 15:17 |
| mntmn | got it to work though | 15:38 |
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| Guest78 | ilia__s .. Thanks, I did try that, and had the same ld, problem :-/ | 16:58 |
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| ilia__s | here is the env I use which includes litex and riscv toolchain and targets vexriscv: https://github.com/sergachev/litex-template | 20:30 |
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