| *** tpb <[email protected]> has joined #litex | 00:00 | |
| *** Degi_ <[email protected]> has joined #litex | 02:46 | |
| *** Degi <[email protected]> has quit IRC (Ping timeout: 252 seconds) | 02:46 | |
| *** Degi_ is now known as Degi | 02:46 | |
| trabucayre | _florent_: spi is already done | 04:33 |
|---|---|---|
| trabucayre | jtag access is TBD :) | 04:34 |
| *** Emantor <[email protected]> has quit IRC (Ping timeout: 245 seconds) | 06:34 | |
| *** nickoe <[email protected]> has quit IRC (Ping timeout: 245 seconds) | 06:34 | |
| *** Emantor <[email protected]> has joined #litex | 06:36 | |
| *** nickoe <[email protected]> has joined #litex | 06:38 | |
| _florent_ | trabucayre: Thanks, I just tested it and it works perfectly | 07:36 |
| _florent_ | and created https://github.com/trabucayre/openFPGALoader/pull/127 to support the dev kit I'm using | 07:36 |
| *** FabM <[email protected]> has joined #litex | 07:37 | |
| trabucayre | applied now! | 07:39 |
| trabucayre | JTAG support seems straightforward to add -> this weekend (with a bit of luck and time) | 07:40 |
| *** nthiel <[email protected]> has joined #litex | 07:49 | |
| _florent_ | trabucayre: The SPI Flash support is already great, JTAG support would allow us to completely avoid the Efinix programmer (but only do it if it's also useful for you) | 07:58 |
| *** cr1901 <cr1901!~William@2601:8d:8600:911:a046:e1f7:4d70:fe9d> has quit IRC (Ping timeout: 245 seconds) | 08:05 | |
| trabucayre | it's always useful :) | 08:36 |
| trabucayre | (and in my TODO list for a while) | 08:36 |
| trabucayre | I will try it with xyloni. T120 dev kit is a bit too expensive for me | 08:38 |
| _florent_ | trabucayre: Sure, I use the T120 because I also want to play with the LPDDR3, Ethernet and MIPI, but I should also receive a Xyloni next week | 09:08 |
| _florent_ | trabucayre: The interfaces with the FTDI are probably very similar between the different dev kits | 09:08 |
| *** cr1901 <cr1901!~William@2601:8d:8600:911:4167:ef6b:ec8f:a1fb> has joined #litex | 09:10 | |
| trabucayre | for T120 I don't know but xyloni: interfaceA: spi, interfaceB:jtag, interfaceC:uart, interfaceD: bank power (?) | 09:14 |
| trabucayre | I try to integrate xyloni but have an issue with PLL (xml db are a bit different for T8) | 09:15 |
| *** TMM_ <[email protected]> has quit IRC (Quit: https://quassel-irc.org - Chat comfortably. Anywhere.) | 09:36 | |
| *** TMM_ <[email protected]> has joined #litex | 09:36 | |
| *** Guest7894 <[email protected]> has joined #litex | 09:41 | |
| Guest7894 | @_florent_ thanks your fix for setting the ethmac csr map helped me. I was just building xilinx_kc705 extended with a UDPIPCore and a FreqMeter instance | 09:43 |
| Guest7894 | Now after pulling the latest litex, I get a linker error : target emulation `elf64-littleriscv' does not match `elf32-littleriscv' | 09:44 |
| Guest7894 | Google says that the problem could be with march flag being set incorrectly. After looking around soc/cores, I see that the march is set correctly to rv32im for the default vexriscv + standard | 09:46 |
| Guest7894 | targets/build/xilinx_kc705/software/libc/cross.txt .. even has the flag -march=rv32im | 09:49 |
| Guest7894 | not sure what I am missing | 09:49 |
| Guest7894 | _florent_ could this error be related to some flags gone missing in the picolibc update? | 10:13 |
| Guest7894 | I can confirm that with a fresh install of litex, this still happens. I wondered if it has something to do with my RISCV install, but I just followed the steps here: https://github.com/litex-hub/linux-on-litex-vexriscv#installing-a-risc-v-toolchain | 11:11 |
| *** mc6808 <[email protected]> has quit IRC (Quit: Client closed) | 11:27 | |
| *** indy_ <[email protected]> has quit IRC (Ping timeout: 265 seconds) | 13:40 | |
| *** indy <[email protected]> has joined #litex | 13:43 | |
| somlo | _florent_: commit 2c98ad94 ("fhdl/verilog: Create_print_operator/_print_slice, move code...") broke my litex/rocket build (at least) on nexys4ddr: https://pastebin.com/6DXCUBFG | 14:38 |
| tpb | Title: ****** Vivado v2018.2 (64-bit) **** SW Build 2258646 on Thu Jun 14 20:02:38 M - Pastebin.com (at pastebin.com) | 14:38 |
| somlo | _florent_: my command line is "litex-boards/litex_boards/targets/digilent_nexys4ddr.py --build --cpu-type rocket --cpu-variant linux4 --sys-clk-freq 50e6 --with-ethernet --with-sdcard" | 14:39 |
| *** FabM <FabM!~FabM@armadeus/team/FabM> has quit IRC (Quit: Leaving) | 14:46 | |
| *** nthiel <[email protected]> has quit IRC () | 15:01 | |
| _florent_ | somlo: Thanks, sorry for this, I'm going to look at it | 19:33 |
| _florent_ | somlo: It should be fixed with https://github.com/enjoy-digital/litex/commit/306bdcaed8e7a548e33db924a9312a9d39909ee7 | 19:49 |
| somlo | _florent_: thanks, it looks like it's building OK now | 20:21 |
| *** TMM_ <[email protected]> has quit IRC (Quit: https://quassel-irc.org - Chat comfortably. Anywhere.) | 22:34 | |
| *** TMM_ <[email protected]> has joined #litex | 22:34 | |
| Guest7894 | Hi All, what is the current recommended way to install riscv toolchain for vexriscv+standard ? | 23:02 |
| *** C-Man <[email protected]> has joined #litex | 23:27 | |
Generated by irclog2html.py 2.17.2 by Marius Gedminas - find it at https://mg.pov.lt/irclog2html/!