Monday, 2021-10-11

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tcalAm I naive for hoping that I could get DDR litespi running on a Fomu by just adding "rate='1:2'" to `self.add_spi_flash(....)` in litex_boards/targets/kosagi_fomu.py? 00:20
NotHetOk so I am thinking a lot of the Zephyr LiteX drivers were broken by the switch to the 32 bit CSR bus. 00:36
NotHetNeeding partial re-writes: hwinfo_litex.c, eth_liteeth.c, litex_timer.c; Ok if soc/riscv/litex/soc.h were fixed: gpio_litex.c, i2c_litex.c, i2s_litex.c, pwm_litex.c, uart_liteuart.c; not sure clock_control_litex.c00:37
NotHetIs setting csr_data_width to 8 a resonable idea for Zypher? 00:59
NotHetNope, that doesn't work. Gives an assertion error.01:28
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tcalDDR on Fomu doesn't work out of the box by just adding `rate='1:2'`; the error message is `ERROR: Unable to find a placement location for cell 'SB_IO_13'`.   This is the IO structure that's generated:01:46
tcalhttps://www.irccloud.com/pastebin/VEo8LxW6/fomu%20ddr%20io01:46
tpbTitle: Snippet | IRCCloud (at www.irccloud.com)01:46
tcal`
builder_inferedddrtristate2__i` connects those two SB_IO instances, from(?) one's `PACKAGE_PIN` to the other's `D_IN_0`.01:48
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cr1901_florent_: I'm going to ask a question, and you're not going to like it :). Since it appears we now have a dep on meson thanks to picolibc, are there any potential plans to rip out the Makefile completely and use meson to build all the software :) (and maybe even the gateware :o)?04:43
cr1901(This is not an entirely serious suggestion, btw. But I'm probably going to do a round of Windoze compat patches soon, and it was on my mind.)04:46
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_florent_cr1901: This could be worth having a look at it in the long term yes (but using Makefile is also nice to simplify integration with other software relying on it, ex MicroPython).06:40
_florent_NoHet: I thought Zephyr drivers were already using 32-bit CSRs, if it's not the case, it would be interesting to do the switch as we did in the Linux drivers06:41
_florent_NoHet: I just verified and the recent LiteEth changes do not introduce a CSR mapping change. So the issue in Zephyr seems to be only related to the CSR data-width07:14
_florent_Note that you the default has changed in LiteX, but you can still pass --csr-data-width=8 to use 8-bit CSR data-width SoCs07:15
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acathlaThe actual litex wants to use picolibc but fails, how do I force the use of the old libc?13:10
acathlaMeanwhile, I did a checkout on an old litex (23sept) and it works fine again13:19
cr1901I know riscv and power get most of the love lately, but is there a way to ensure e.g. a lm32 SoC still builds (picolibc doesn't support lm32 yet)13:38
cr1901?13:38
NotHet_florent_: Looks like 8 bit CSR was/is broken? https://github.com/enjoy-digital/litex/commit/4ee9c53f185ac6dd9c4aa69a7547e9bc037acc25 . Removing the assert the SOC will build, but the bios hangs in spiflash_core_master_status_rx_ready_read. 13:53
NotHetI am thinking I will try to fix Zephyr drivers for 32 bit CSR. Probably two weeks+ to complete.  I am most worried about test, I have a single HW platform with limited peripherals. 13:53
NotHetHaving someone I can bother with questions about the drivers would be good too, is there someone willing? I see most drivers are authored by AntMicro.13:53
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tntWhy do some platform do platform.add_period_constraint(self.cd_sys.clk, 1e9/sys_clk_freq)  and some don't ?14:24
tnthttps://pastebin.com/6Trat0Cr14:24
tpbTitle: class CRG(Module): def __init__(self, platform, sys_clk_freq): sel - Pastebin.com (at pastebin.com)14:24
tntThat's the CRG I'm using ATM but looking at timing report it seems it analyzed nothing ...14:24
tntso I'm guessing I might need it but I thought the USMMCM knowing the input/output freq would deal with that.14:25
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_florent_acathla, cr1901: All the different supported CPU have been tested with picolibc (this was a condition to use it), so it should still work, if not can you describe the issue?14:55
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_florent_NoHet: The Zephyr drivers are indeed maintained by Antmicro, could you open an issue in LiteX to describe the issues? and I'll make sure you can discuss with them14:57
_florent_tnt: If you input clk has a timing constraint, it should propagate through the PLL/MMCm14:58
_florent_tnt: you can do something similar to https://github.com/litex-hub/litex-boards/blob/master/litex_boards/platforms/xilinx_kc705.py#L551 in your Platform15:00
tnt_florent_: ok, so I guess that's what I'm missing. 15:00
_florent_tnt: but yes, it's possible we still have some inconsistencies between platforms/targets on timing constraints15:01
tnt_florent_: btw, I found a working clock on that board ... there is an ad9542 which is also a programmable pll but it's configured to auto-load its config from an i2c eeprom :)15:01
_florent_tnt: ah good, this will probably be a bit more accurate than the internal osc :)15:03
acathla_florent_, error log here : https://pastebin.com/CzyuxSye15:09
tpbTitle: Litex and picolibc error - Pastebin.com (at pastebin.com)15:09
tntMmm, I was hoping platform.add_false_path_constraints(self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk)   would do the trick, but it's still analysin across :/15:22
tntErr ... how do I include {} in custom plaform commands ? They get interpreted by python at some step in the process ...15:46
leonsflorent: I've seen on your twitter that you have gotten SPF+ modules working with the FPGAs. Do you by chance know whether there's any extra setup required (besides deasserting the TX_DISABLE pin) compared to using DACs?15:55
jevinskie[m]Add more {}, you really have to throw them in there :)15:55
leonsOn my FPGA I have 10G Ethernet working using a DAC just fine, but on optical modules I don't get a carrier. My other device does indicate some receive signal power though15:55
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_florent_acathla: can you try to install meson with pip3 install meson to have a recent version?16:42
_florent_leons: The optical module should operate correctly with just tx_disable set correctly, no extra setup is required16:47
_florent_leons: But check the polarity of tx_disable, it's sometimes inverted on the board16:48
tntif the remote sees power, it should be good.16:48
acathla_florent_, it works!16:48
acathlaThanks. 0.53.2-2ubuntu2 vs 0.59.216:59
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tnt"Memory initialization failed "17:57
tntAh well, would have been too good if it works first time :)17:57
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tntQuestion is of course: how does one even debug that :/18:04
tnthttps://pastebin.com/j5DZtGhE18:05
tpbTitle: Initializing SDRAM @0x40000000... - Pastebin.com (at pastebin.com)18:05
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tntDoes anyone have a working DDR4 calib just to see what a good one is supposed to look like ?19:11
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_florent_tnt: have you set the INTERNAL_VREF constraints on the DRAM banks?20:21
_florent_ex: https://github.com/litex-hub/litex-boards/blob/master/litex_boards/platforms/xilinx_zcu104.py#L121-L12320:21
tnt_florent_: I have not.20:24
_florent_This probably explains the behaviur. On DDR4 these constraints a really mandatory.20:25
tntTrying it now.20:27
_florent_here is an log of a working calibration:20:27
_florent_https://hastebin.com/foradezoha.yaml20:27
tpbTitle: hastebin (at hastebin.com)20:27
tnt`Memtest OK`  \o/20:32
tntThanks !20:32
tntAnd the other ddr4 bank works too. Perfect.20:41
tntI guess the next step is PCIe.  I got it to build but it's seemingly doing nothing.20:41
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