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| Melkhior | Pictures of the SBusFPGA V1.2 are online: <https://github.com/rdolbeau/SBusFPGA/tree/main/Pictures> | 09:51 |
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| _florent_ | Melkhior: Thanks, that's a very nice project | 10:45 |
| Melkhior | _florent_: thanks! | 10:54 |
| Melkhior | BTW, any known issue with sdcard & linux at the moment? Trying the micro-sd card slot on my board, and it still won't write and I don't understand why :-( | 10:54 |
| Melkhior | mounting and reading are fine, writing fails | 10:55 |
| Melkhior | well, it's not Litex ; same SW, same configuration except with the pins routed to the pmod ... and the micro-sd card write just fine | 11:06 |
| Melkhior | I don't understand what I could have messed up when implementing the micro-sd ! | 11:06 |
| Melkhior | grrr, if you just say 'pullup' does it mean 'pullup false' in the Xilinx properties ? | 11:29 |
| Melkhior | because I just added some 'true' to be cleaner, and now it seems my micro-sd card works! | 11:30 |
| Melkhior | Also if anyone is interested in a low-pin-count, low-color accuracy VGA Pmod, mine is here: <https://github.com/rdolbeau/SBusFPGA/tree/main/VGA222-PMOD> | 11:40 |
| _florent_ | Melkhior: possible for pullup, we are using PULLUP True in the platforms: https://github.com/litex-hub/litex-boards/blob/master/litex_boards/platforms/digilent_arty.py#L302 | 11:42 |
| Melkhior | yes, I saw that and that's why I added 'True' just to be clean before doing a PR for the updated board ... | 11:44 |
| Melkhior | I should have read UG912 ... | 11:45 |
| Melkhior | "FALSE|NO: Do not use a pullup circuit (default)." | 11:45 |
| Melkhior | grrr | 11:45 |
| Melkhior | Well, hopefully I can learn from my mistakes ... | 11:47 |
| Melkhior | In which case i'm learning a lot :-) | 11:47 |
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| Wolf0 | Anyone who knows memory well know what an RDQS window is? | 17:12 |
| Wolf0 | *RDQS window status | 17:12 |
| Wolf0 | Or, valid window status (or not valid, I guess) | 17:19 |
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| _florent_ | Wolf0: I'm not very familiar with the lower layers of HBM, but for the reads, there is probably a calibration of the DQS signal (Clk for the Data) to ensure an optimal Data sampling. The valid window is probably the window for which the data is sampled correctly and the ideal sampling point is in the middle. | 18:36 |
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